mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 31

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
9. Burst in bank n continues as initiated.
represented by the current state only.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m burst.
charge), the READ to bank m will interrupt the READ on bank n, CL later.
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with the
data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
charge), the WRITE to bank will interrupt the WRITE on bank n when registered. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered.
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered.
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered one clock prior to the READ to bank m.
the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to
bank n will begin after
tered. The last valid WRITE to bank n will be data registered one clock to the WRITE to
bank m.
t
WR is met, where
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR begins when the WRITE to bank m is regis-
t
WR is met, where
©2008 Micron Technology, Inc. All rights reserved.
Operations
Preliminary
t
WR