mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 37

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 14:
Operating Mode
Write Burst Mode
Extended Mode Register (EMR)
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
CAS Latency
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.
When M9 = 0, the BL programmed via M[2:0] applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
The EMR controls the functions beyond those controlled by the mode register. These
additional functions are special features of the mobile device that helps reduce overall
system power consumption. They include temperature-compensated self refresh
(TCSR) control, partial-array self refresh (PASR), and output drive strength.
The EMR is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and
retains the stored information until it is programmed again or the device loses power.
Command
Command
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CL = 2
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
NOP
NOP
T1
T1
37
t
t AC
LZ
CL = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
Don’t Care
T3
T3
NOP
D
t OH
OUT
Undefined
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
T4
Preliminary