mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 39

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Output Drive Strength
Bank/Row Activation
Figure 16:
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
Example: Meeting
4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0)
5. Quarter bank (bank 0; BA1 = BA0 = row address MSB - 1 = 0)
WRITE and READ commands occur to any bank selected during standard operation, but
only the selected banks or segments of a bank in PASR are refreshed during self refresh. It
is important to note that data in unused banks or portions of banks is lost when PASR is
used.
Because the Mobile DDR SDRAM is designed for use in smaller systems that are typically
point-to-point connections, an option to control the drive strength of the output buffers
is provided. Drive strength should be selected based on the expected loading of the
memory bus. There are four supported settings for the output drivers: 25Ω, 37Ω, 55Ω,
and 80Ω internal impedance. These are full, three-quarter, one-half, and one-quarter
drive strengths, respectively.
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, that
selects both the bank and the row to be activated (see Figure 16 on page 39).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 16 on page 39, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
Command
RRD.
CLK
t
RCD (MIN) When 2 <
ACTIVE
T0
t CK
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
t
NOP
RCD (MIN)
T1
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
39
t CK
t
CK ≤ 3. (The same procedure is used to convert other
t
RCD specification.
t
RCD (MIN)/
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
t CK
t
CK < 3
READ or
WRITE
Don’t Care
t
RCD (MIN) should be divided by
T3
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
Preliminary
t
RC.