mt48h8m16lf Micron Semiconductor Products, mt48h8m16lf Datasheet - Page 43

• Manufacturer Part Number: mt48h8m16lf
• Description: 128mb 8 Meg X 16, 4 Meg X 32 Mobile Sdram
• Manufacturer: Micron Semiconductor Products

Figure 19:
PDF: 09005aef832ff1ea / Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr5.08__4.fm - Rev. B 6/08 EN
READ-to-WRITE
Notes:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 18 on
page 42 shows the case where the clock frequency provides for bus contention to be
avoided without adding a NOP cycle, and Figure 20 on page 44 shows the case where the
additional NOP is needed.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated). The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 21 on page 44 for
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. However, the advan-
tage of the PRECHARGE command is that it can be used to truncate fixed-length or
continuous page bursts.
1. CL = 3. The READ command may be to any bank, and the WRITE command may be to any
Command
Address
bank. If a burst of one is used, then DQM is not required.
DQM
CLK
DQ
T0
Bank,
READ
Col n
Transitioning Data
T1
NOP
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
T2
NOP
43
t
RP is met. Note that part of the row precharge time is
T3
NOP
D
t
OUT
HZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CK
n
Don’t Care
T4
WRITE
Bank,
Col b
D
IN
b
t
DS
©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Preliminary