AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 11

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
3.6
This group includes all the GPIO pins, many of which are multiplexed with other functions. The default function of
GPIO pins after reset is specified by PM[FF:F4 and D3:C0]. When programmed as GPIOs, these pins are capable of
being programmed to be inputs or push-pull outputs. GPIO pins remain functional during sleep states (if they are
powered).
Pin name and description
C32KHZ. 32.768 kHz clock output. This pin may also be configured as
GPIO15 by PMCF.
CACHE_ZZ. Level 2 cache sleep mode output. This is designed to be
connected to the power-control input to the second level cache to place it
into low-power mode. It is controlled by C3A50. This pin may also be
configured as GPIO8 by PMC8.
CPUSLEEP#. Processor non-snoop sleep mode output. This may be
connected to the sleep pin of the processor to place it into a non-snoop-
capable low-power state. It is controlled by C3A50. This pin may also be
configured as GPIO5 by PMC5.
CPUSTOP#. Processor clock stop output. This may be connected to the
system clock chip to control the host clock signals. It is controlled by
C3A50. This pin may also be configured as GPIO6 by PMC6.
DCSTOP#. DRAM controller stop output. This may be connected to the
system memory controller to indicate that its clock is going to stop (so that
an alternative DRAM refresh scheme may start). It is controlled by
C3A50. This signal is also functional during STD, STR and SOFF.
EXTSMI#. External SMI input. This pin may be used to generate SMI
or SCI interrupts and resume events. This pin may also be configured as
GPIO12 by PMCC.
FLAGRD#. Flag read output. This may be connected to the output-
enable input of external buffers with the buffer outputs on the SD pins.
Therefore, the inputs to the buffers may be software-readable flags.
FLAGRD# is asserted during reads of PM1A. This pin may also be
configured as GPIO11 by PMCB.
FLAGWR. Flag write output. This may be connected to the latch-
enabled input of external latches with the latch inputs on the SD pins.
Therefore, the outputs of the latches may be software-controlled flags.
FLAGWR is asserted during writes to PM18. This pin may also be
configured as GPIO10 by PMCA.
System Management Signals
Preliminary Information
AMD-766
TM
Output,
Output,
Output,
Output,
Output,
Output,
Output,
IO cell
Input,
type
IO
IO
IO
IO
IO
IO
IO
IO
Peripheral Bus Controller Data Sheet
VDD3
VDD3
VDD3
VDD3
VDD_
VDD_
VDD3
VDD3
Power
plane
AUX
AUX
During
Active
Reset
High
High
High
Low
Low
Low
-
Reset
High
High
High
High
Post
Low
Low
Low
-
Func.
Func.
Func.
Func.
Func.
High
POS
Low
-
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