AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 36

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
C0A43: ROM Decode Control Register
Configuration space; function 0; offset: 43h Default: 00h Read-write.
This register specifies the address space mapped to the BIOS ROM on either the ISA bus or the LPC bus (based on
the state of C3A48[ISABIOS]). The ROM_KBCS# pin is used to enable accesses to the system BIOS on the ISA bus.
LPC bus accesses are decoded by the LPC BIOS device with the LPC address map shown below.
7:0
SEGEN
SEGEN. ROM segment enables. For each of these bits: 1=Enables the specified address range as a BIOS ROM
access. 0=The specified address range is not decoded as a BIOS ROM access. These bits control the following
address ranges; the last column shows the translated LPC bus addresses if C3A48[ISABIOS]=0; the next column
shows the translated ISA bus address if C3A48[ISABIOS]=1:
SEGEN
Note: The following ranges are fixed BIOS address ranges:
Note: See C0A80 for further information about how access to BIOS spaces is controlled.
C0A46: Miscellaneous Control 1 Register
Configuration space; function 0; offset: 46h Default: 00h Read-write.
7
Reserved
PMWE. Posted memory write enable. 1=Enable the one-DWORD write buffer from PCI target memory writes to
the ISA/LPC bus. 0=The IC waits until the ISA/LPC cycle is complete before passing ready back to the PCI bus.
C0A47: Miscellaneous Control 2 Register
Configuration space; function 0; offset: 47h Default: 00h
7
CPURS
SWPCIR. Software PCI reset. Write only. When this bit is written with a 1, a 1.5 to 2.0 millisecond reset pulse is
generated over PCIRST# and CPURST#.
PCIDTEN. PCI delayed transaction enable. Read-write. 1=PCI accesses that target the ISA/LPC bus and internal
legacy registers utilize delayed-transactions. 0=PCI accesses that target the ISA/LPC bus and internal legacy
registers are terminated after the ISA/LPC bus cycle is complete. This bit does not affect posted memory writes
(C0A46[PMWE]=1), for which always disconnect with data. Note: When PCIDTEN=0, the state of
C0A4A[PGNT1ST] is ignored and the IC always waits for the PCI bus to be granted to the LPC DMA/master state
machine before asserting the DACK# signal. It is expected that PCIDTEN is normally set high.
CPURS. CPU reset select. Read-write. 1=Processor resets are directed toward the INIT# pin. 0=Processor resets
are directed toward the CPURST# pin. This bit is required to be high.
bit
0
1
2
3
4
5
6
7
4 megabytes FFC0_0000 - FFFF_FFFFh
1 megabyte FFB0_0000 - FFBF_FFFFh
32K bytes
32K bytes
32K bytes
32K bytes
32K bytes
32K bytes
64K bytes
64K bytes
Size
Size
6
PCIDTEN
6
Reserved
PCI Address Range[31:0]
000C_0000 - 000C_7FFFh
000C_8000 - 000C_FFFFh
000D_0000 - 000D_7FFFh
000D_8000 - 000D_FFFFh
000E_0000 - 000E_7FFFh
000E_8000 - 000E_FFFFh
PCI Address Range[31:0]
000F_0000 - 000F_FFFFh
FFFF_0000 - FFFF_FFFFh
5
Reserved
5
Reserved
4
Reserved
4
Reserved
Preliminary Information
FD_0000 - FD_7FFFh
FD_8000 - FD_FFFFh
FE_0000 - FE_7FFFh
FE_8000 - FE_FFFFh
Address translation
for ISA bus[23:0]
FC_0000 - FC_7FFFh
FC_8000 - FC_FFFFh
B0_0000 - BF_FFFFh
C0_0000 - FF_FFFFh
Address translation
for ISA bus[23:0]
FF_0000 - FF_FFFFh
FF_0000 - FF_FFFFh
3
Reserved
3
Reserved
AMD-766
2
Reserved
2
Reserved
TM
Peripheral Bus Controller Data Sheet
FFFC_0000 - FFFC_7FFFh
FFFC_8000 - FFFC_FFFFh
FFFD_0000 - FFFD_7FFFh
FFFD_8000 - FFFD_FFFFh
FFFE_0000 - FFFE_7FFFh
FFFE_8000 - FFFE_FFFFh
FFFF_0000 - FFFF_FFFFh
Address translation
for LPC bus
FFB0_0000 - FFBF_FFFFh
FFC0_0000 - FFFF_FFFFh
Address translation
for LPC bus
FFFF_0000 - FFFF_FFFFh
1
Reserved
1
Reserved
0
PMWE
0
SWPCIR
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