AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 45

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
5.3.3
These timers are halted from counting, if enabled to do so in C3A4C[PIT_DIS], when PRDY is asserted.
The following are ports used to access the legacy PIT:
PORT43: PIT Control Byte Register
Fixed IO space; offset: 43h. Default: 00h. Write only.
Offset
Bits
40h
41h
42h
43h
7:6
5:4
3:1
0
Legacy Programmable Interval Timer (PIT) Registers
Description
SC[1:0]: select counter. Specifies the counter that the command applies to as follows:
RW[1:0]: read-write command. Specifies the read-write command as follows:
M[2:0]: counter mode. Specifies the mode in which the counter selected by SC[1:0] operates as follows:
BCD: binary coded decimal. 1=Counter specified by SC[1:0] operates in binary coded decimal. 0=Counter
specified by SC[1:0] operates in 16-bit binary mode.
Access Port
Write Counter 0 write access port
Write Counter 1 access port
Write Counter 2 access port
Write Control byte
Read
Read
Read
Read
00b
01b
10b
11b
00b
01b
10b
11b
000b Interrupt on terminal count.
001b Hardware retriggerable one-shot (not supported).
010b Rate generator.
011b Square wave mode.
100b Software triggered strobe.
101b Hardware triggered (retriggerable) strobe (not supported).
110b When this value is written, 010b is stored in the register, rate generator mode.
111b When this value is written, 011b is stored in the register, square wave mode.
Counter 0 read access port
Counter 1 read access port
Counter 2 read access port
Not supported
Counter 0.
Counter 1.
Counter 2.
Read back command.
Counter latch command.
Read/write least significant byte only.
Read/write most significant byte only.
Read/write least significant byte followed by most significant byte.
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
45