AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 48

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
5.3.5
The IOAPIC register set for the 24 IOAPIC interrupts supported by the IC is indexed through two fixed-location,
memory-mapped ports: FEC0_0000h, which provides the 8-bit index register, and FEC0_0010h, which provides the
32-bit data port. Writes to the 32-bit data port at FEC0_0010h require that all four bytes be enabled.
The index register selects one of the following:
Index
00h
01h
02h
10h-3Fh Redirection registers. Each of the 24 redirection registers uses two of these
40h-FFh Reserved.
The redirection registers are defined as follows:
Bits
63:56
55:17
16
15
14
13
12
11
10:8
5.3.6
RTC70: Real-Time Clock Legacy Indexed Address.
IO mapped (fixed); offset: 0070h. Default: 80h. Write only.
Note: RTC70[6:0] and RTC72 occupy the same physical register; after writes to RTC70, RTC72 reads back as {0b,
RTC70[6:0]}; after writes to RTC72, reads of RTC72 provide all 8 bits written.
7
NMIDIS
RTCADDR. Real time clock address. Specifies the address of the real-time clock CMOS RAM. The data port
associated with this index is RTC71. Only the lower 128 bytes of the CMOS RAM are accessible through RTC70
and RTC71.
NMIDIS. NMI disable. 1=PORT61[IOCHK and SERR] are disabled from being able to generate NMI interrupts to
the processor. Note: The state of this register is read accessible through C0A41[NMIDIS].
7:0
IOAPIC Registers
Real-Time Clock Registers
Description
Destination. In physical mode, bits[59:56] specify the APIC ID of the target processor. In logical mode
bits[63:56] specify a set of processors.
Reserved.
Interrupt mask. 1=Interrupt is masked.
Trigger mode. 0=Edge sensitive. 1=Level sensitive.
IRR: interrupt request receipt. Read only. This bit is not defined for edge-triggered interrupts. For level-
triggered interrupts, this bit is set by the hardware after an interrupt is detected. It is cleared by receipt of
EOI with the vector specified in bits[7:0].
Polarity. 0=Active high. 1=Active low.
Delivery status. 0=Idle. 1=Interrupt message pending.
Destination mode. 0=Physical mode. 1=Logical mode.
Delivery mode. 000b=fixed. 001b=Lowest priority. 010b=SMI. 011b=Reserved. 100b=NMI. 101=Init.
110b=Reserved. 111b=ExtINT.
Interrupt vector.
Description
APIC ID register. The ID is in bits[27:24]. All other bits are reserved.
IOAPIC version register.
IOAPIC arbitration ID register. The ID is in bits[27:24]. All other bits
are reserved.
indexes. Bits[63:32] are accessed through the odd indexes and bits[31:0] are
accessed through the even indexes.
6:0
RTCADDR
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
Attribute
Read-write
Read only
Read only
Read-write
Default
0000 0000h
0017 0011h
0000 0000h
0000 0000
0001 0000h
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