AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 60

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
PWRFL_STS. Power failure status. Read; updated by hardware; write 1 to LSB to reset to 4h. If power fails
(system enters MOFF or PWRGD goes from 1 to 0 while PWRON# is asserted), then this register captures and
retains the state the system was in when the failure occurred. This field resides on the VDD_AL plane. This field
defaults to 4h when VDD_AL becomes valid. Writing a one to C3A43[3] sets this field to 4h; writing a zero to
C3A43[3] or writing any value to any other bits in this field has no effect. This field is encoded as follows:
G3TOS5. Mechanical off (G3) to soft off (S5). Read-write. 0=When power is a applied to the VDD_AUX plane,
the system automatically transitions to the FON state. 1=When power is a applied to the VDD_AUX plane, the
system enters the SOFF state. This bit resides on the VDD_AL power plane. When VDD_AL becomes valid, this bit
defaults to 0. When there is a PCIRST# generated by a write to PORTCF9[RSTCMD, SYSRST] == 11b, then this is
cleared.
VDDA_STS. VDD_AL reset status. Read; set by hardware; write 1 to clear. 1=VDD_AL became invalid. This bit
resides on the VDD_AL power plane.
C3A44: PNP IRQ Select Register
Configuration space; function 3; offset: 45-44h. Default: 0000h. Read-write.
Bits[11:0] assign PNPIRQ[2:0] pins to IRQs that are routed to interrupt controllers. See section 4.3.4.1 for more
details.
15
TCO_INT_EN
IRQ0SEL. PNPIRQ0 interrupt select. This selects the IRQ number for PNPIRQ0. IRQ0, IRQ2, IRQ8, and IRQ13
are reserved. If PMD2 does not select the PNPIRQ0 function then this field has no effect.
IRQ1SEL. PNPIRQ1 interrupt select. This selects the IRQ number for PNPIRQ1. IRQ0, IRQ2, IRQ8, and IRQ13
are reserved. If PMD3 does not select the PNPIRQ1 function then this field has no effect.
IRQ2SEL. PNPIRQ2 interrupt select. This selects the IRQ number for PNPIRQ2. IRQ0, IRQ2, IRQ8, and IRQ13
are reserved. If PMF4 does not select the PNPIRQ2 function then this field has no effect.
TCO_INT_SEL. TCO interrupt select. Specifies the IRQ line asserted by either PM46[INTRDR_STS] (if
PM4A[INTRDR_SEL] selects IRQ) or PM44[TCO_INT_STS]. Note: If PM22[TCOSCI_EN] is set, then this field
is has no effect. Note: if one of IRQ[11:9] is selected, then the PIC is required to be programmed as level sensitive
for this interrupt. This field is encoded as follows:
TCO_INT_EN. TCO interrupt enable. 1=Enable TCO IRQ selected by C3A44[TCO_INT_SEL] (if
PM22[TCOSCI_EN] = 0).
C3A46: PNP DMA and Chip Select Register
Configuration space; function 3; offset: 47-46h. Default: 0000h. Read-write.
15
Reserved
7
Reserved
CS0IO. PNPCS0# IO space selection. 1=PNPCS0# is asserted during accesses to the IO addresses specified by
programmable IO range monitor 3 (C3A46[CS0UBM], C3AC8, and C3ACC) and PCI accesses to this range are
claimed by the IC and routed to the ISA bus. If the PNPCS0# function is not selected by PMF6, then this bit has no
effect.
TCO_INT_SEL Interrupt
PWRFL_STS Power state
0h
1h
2h
3h
0
1
2
3
14
Reserved
6:4
Reserved
FON full on
POS power on suspend
C2
C3
14:12
TCO_INT_SEL IRQ2SEL
IRQ9
IRQ10
IRQ11
Reserved
13
Reserved
11:8
12
CS1UBM
Preliminary Information
11
3
CS1MEM
CS0UBM
PWRFL_STS Power state
TCO_INT_SEL Interrupt
7:4
IRQ1SEL
4h
5h
6h
7h
AMD-766
4
5
6
7
10:9
IRQ12_SEL
2
CS1IO
No AC power failure
STR suspend to RAM
STD suspend to disk
SOFF soft off
TM
APIC IRQ20
APIC IRQ21
APIC IRQ22
APIC IRQ23
Peripheral Bus Controller Data Sheet
1
CS0MEM
3:0
IRQ0SEL
8
Reserved
0
CS0IO
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