AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 18

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
4.3.4
The IC includes two interrupt controllers: the legacy PIC and an IOAPIC. Interrupt sources are routed to the
interrupt controllers as shown in the following diagram.
4.3.4.1
Vectored interrupt requests are routed to the legacy
PIC and APIC as shown. The interrupt signals to the
PIC may be either rising-edge triggered or active-low
level triggered. It is expected that edge-triggered
interrupts such as IRQ14 from the IDE controller rise
into the PIC to indicate the presence of an interrupt.
Conversely, level-sensitive interrupts are low into the
PIC to indicate the presence of an interrupt. Edge and
level sensitivity for each IRQ are programmed into the
PIC through PORT4D0.
The internal USB interrupt signal drives the PIRQD# pin low as an output; when the USB interrupt is deasserted,
PIRQD# is left in the high impedance state. So the USB interrupt is wired-ORed into the active state with external
interrupts on PIRQD#. The result enters the IC and goes to the interrupt routing logic.
The following are the interrupt routing logic equations:
NMI, INIT
SMI
SCI
IRQ pins, TCO,
PNPIRQ[2:0],
serial IRQ
PIRQ[D:A]#
GPIO[17, 16, 3, 2 ]
Interrupt Controllers
Interrupt Routing Logic
Interrupt
routing
logic
Preliminary Information
Legacy
USB_INT
PIRQ[D:A]#
PNPIRQ[2:0]
SCI_IRQ
IRQx (from ISA bus)
Serial IRQs
redirection
PIC
registers
24
AMD-766
Interrupt pins
INTR
to the host
IOAPIC
TM
Peripheral Bus Controller Data Sheet
Interrupt
Routing
APIC interrupt
Logic
message bus
PIC_IRQx
PORTD0
IOAPIC
PIC
18