AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 44

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
5.3.2
The legacy DMA controller (DMAC) in the IC supports the features required by the LPC I/F Specification Revision
1.0, which are a subset of the features in legacy DMA Controllers. Single, demand, verify, and increment modes are
supported. Block, decrement, cascade modes are not supported. Also, memory-to-memory transfers and external
EOPs (end of process) are not supported.
There are 7 supported DMA channels. Channels 0-3 support 8-bit transfers. Channels 5-7 support 16-bit transfers.
There is no support for 32-bit DMA transfers. LPC master device requests are made using channel 4.
Although not all registers of legacy DMA controllers are supported, the IO address locations for the unsupported
registers is consistent with legacy logic. The implemented DMAC registers are listed in the following table.
Name
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Status Registers
Command Registers
Mode Registers
Mask Registers
Note 1: although channel 4 base and current registers exist for compatibility, they are not used.
Note that not all bits in the command and mode registers of legacy DMA controllers are implemented in the IC’s
DMA controller. The bit usage for these registers are as follows.
Command registers (master and slave DMAC)
Mode registers (master and slave DMAC)
Note: DMA channel 4 is hard-wired into cascade mode; however cascade mode is obsolete for all other channels.
Bit Legacy DMAC function
Bit Legacy DMAC function
7:6 00b Demand mode select
3:2 00b Verify transfer
1:0 Channel select
7
6
5
4
3
2
1
0
5
4
DACK sense
DREQ sense
Late/Extended write
Fixed/Rotating priority
Normal/Compressed timing
Controller enable/disable
Ch0 address hold enable/disable
Memory-to-memory enable/disable
01b Single mode select
10b Block mode select
11b Cascade mode select
Address increment/decrement select
Auto initialization enable/disable
01b Write transfer
10b Read transfer
11b Illegal
Legacy DMA Controller (DMAC) Registers
Size
16 bits
16 bits
16 bits
16 bits
8 bits
1 bit
5 bits
4 bits
Number
8
8
8
8
2
2
8
Obsolete
Obsolete
Obsolete
Obsolete (always fixed priority)
Obsolete
Controller enable/disable
Obsolete
Obsolete
DMAC function of the IC
00b Demand mode select
01b Single mode select
10b Obsolete
11b Obsolete (see note)
Obsolete (always increment)
Auto initialization
enable/disable
00b Verify transfer
01b Write transfer
10b Read transfer
11b Illegal
Channel select
Preliminary Information
DMAC function of the IC
2
Comments
1 for each channel (0-7) (see note 1)
1 for each channel (0-7) (see note 1)
1 for each channel (0-7) (see note 1)
1 for each channel (0-7) (see note 1)
1 for Master and 1 for Slave DMAC
1 for Master and 1 for Slave DMAC
1 for each channel (0-7) (see note 1)
1 for Master and 1 for Slave DMAC
AMD-766
TM
Peripheral Bus Controller Data Sheet
44