AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 35

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
C0A41: ISA Bus Control 2 Register
Configuration space; function 0; offset: 41h Default: 02h
7
MBL
SHEN. Shadow register access enable. Read-write. 1=Shadowed IO access to legacy write-only registers is enabled.
0=Normal access of legacy registers. The following table specifies all registers affected by this bit:
IO port
DMA: 00h, 02h, 04h, 06h,
C0h, C4h, C8h, CCh
DMA: 01h, 03h, 05h, 07h,
C2h, C6h, CAh, CEh
DMA: 08h/D0h
DMA: 09h/D2h, 0Ah/D4h,
0Bh/D6h
DMA: 0Ch/D8h, 0Dh/DAh,
0Eh/DCh
DMA: 0Fh/Deh
PIT: 40h
PIT: 41h
PIT: 42h
PIC: 20h
PIC: 21h
PIC: A0h
PIC: A1h
NMIDIS. NMI disable. Read only. This provides read access to RTC70[NMIDIS].
P92FR. Port 92 fast reset. Read-write. 1=Writes that attempt to set PORT92[0]—the fast CPU reset bit—are
enabled. 0=Writes to PORT92[0] are ignored.
MBL. Must be low. Read-write. This bit is required to be low at all times; otherwise undefined behavior will result.
6
Reserved
5
P92FR
R/W Normal mode
W Base address for DMA channel
W Base byte count for DMA channel
W Command Register DMA CH[3:0]/[7:4]
W See DMA controller
W See DMA controller
W Write all masks [3:0]/[7:4]
R
R
R
R
R
R
R
R
R
R
R
Current address for DMA channel
Current byte count for DMA channel
Status Register DMA CH[3:0]/[7:4]
Reserved
Status byte counter 0
Status byte counter 1
Status byte counter 2
Interrupt request register for PIC 1
In service register for PIC 1
Interrupt request register for PIC 2
In service register for PIC 2
4
Reserved
Preliminary Information
3
Reserved
AMD-766
2
Reserved
Shadow mode
Current address for DMA channel
Base address for DMA channel
Current byte count for DMA channel
Base byte count for DMA channel
Status Register DMA CH[3:0]/[7:4]
1
2
3
4
5
6
Reserved
Same as normal mode
Write all masks [3:0]/[7:4]
Read all masks [3:0]/[7:4]
1
2
3
4
5
6
7
Status byte counter 1
Status byte counter 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
In service register for PIC 1
Interrupt request register for PIC 2
In service register for PIC 2
TM
st
nd
rd
th
th
th
st
nd
rd
th
th
th
th
st
nd
rd
th
th
th
th
th
th
th
th
th
th
th
read: Command reg DMA CH[3:0]/[7:4]
read: Status byte counter 0
read: ICW1 for controller 1
read: Mode register DMA CH1/5
read: Mode register DMA CH2/6
read: Mode register DMA CH3/7
read: CRL for counter 1
read: CRM for counter 1
read: CRL for counter 2
read: CRM for counter 2
read: ICW4 for controller 1
read: OCW1 for controller 1
read: OCW2 for controller 1
read: OCW3 for controller 1
read: ICW1 for controller 2
read: ICW2 for controller 2
read: Mode register DMA CH0/4
read: CRM for counter 0
read: ICW3 for controller 1
read: Request reg DMA CH[3:0]/[7:4]
read: CRL for counter 0
read: ICW2 for controller 1
read: ICW3 for controller 2
read: ICW4 for controller 2
read: OCW1 for controller 2
read: OCW2 for controller 2
read: OCW3 for controller 2
Peripheral Bus Controller Data Sheet
1
NMIDIS
0
SHEN
35