AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 68

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
C3AD8: Programmable Memory Range Monitor Trap Mask Registers
Configuration space; function 3; offset: DB-D8h. Default: 0000_0000h. Read-write.
31:16
MASKMEM2
MASKMEM[1,2]. Address mask for the PMEMRM[1,2] trap events. See C3AD0 for details.
5.9
These registers are in IO space. The base address register for these registers is C3A58. See section 5.1.2 for a
description of the register naming convention.
PM00: Power Management 1 Status Register
IO mapped (base pointer: C3A58); offset: 01-00h. Default: 0000h. Read; set by hardware; write 1 to clear.
Most of these bits have the ability to generate an SCI/SMI interrupt, if they are enabled to do so in PM02.
15
WAK_STS
7:6
Reserved
TMR_STS. ACPI timer status. 1=The MSB of the ACPI timer (either bit 23 or 31 based on C3A41[3]), PM08,
toggled (from 0 to 1 or 1 to 0).
BM_STS. Bus master status. 1=One of the PCI REQ# signals (brought in on IRQ[11:9, 7:3]) or BMREQ# or any
internal PCI master requests signals was asserted.
GBL_STS. Global status. 1=PM2C[BIOS_RLS] was set high.
PWRBTN_STS. Power button status. 1=PWRBTN# has been asserted. The debounce circuitry causes a 12-to-16
millisecond delay from the time the input signal stabilizes until this bit changes. If PM26[PBOR_DIS] is low and
PWRBTN# is held low for more than four seconds, then this bit is cleared and PBOR_STS is set. This bit resides on
the VDD_AUX power plane. Note: The debounce circuit functions in the high-to-low and low-to-high directions.
SLPBTN_STS. Sleep button status. 1=SLPBTN# has been asserted. The debounce circuitry causes a 12-to-16
millisecond delay from the time the input signal stabilizes until this bit changes. If the GPIO debounce circuitry
specified by PMC3 is enabled, then the debounce period is twice as long before setting the status bit. If the
SLPBTN# function is not selected by PMC3, then this bit cannot be set. If PM26[SBOR_DIS] is low and SLPBTN#
is held low for more than four seconds, then this bit is cleared and PBOR_STS is set. This bit resides on the
VDD_AUX power plane. Note: The debounce circuit functions in the high-to-low and low-to-high directions.
RTC_STS. Real time clock status. 1=The real-time clock generated an interrupt. This bit resides on the
VDD_AUX power plane.
PBOR_STS. Power button override status. 1=A power button override event occurred. A power button override
event occurs if (1) PM26[PBOR_DIS] is low and PWRBTN# is held in the active state for more than four seconds or
(2) if PM26[SBOR_DIS] is low, the SLPBTN# function is enabled by PMC3, and SLPBTN# is held in the active
state for more than four seconds. This bit resides on the VDD_AUX power plane.
WAK_STS. Wakeup status. 1=The system was in a sleep state (S1 to S5) and an enabled resume event occurred.
Upon setting this bit, the system resumes.
System Management IO Mapped Registers (PMxx)
14:12
Reserved
5
GBL_STS
4
BM_STS
Preliminary Information
15:0
MASKMEM1
11
PBOR_STS
3:1
Reserved
AMD-766
10
RTC_STS
TM
Peripheral Bus Controller Data Sheet
9
SLPBTN_STS PWRBTN_STS
8
0
TMR_STS
68