AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 42

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
5.3
5.3.1
These registers are in IO space at fixed addresses. See section 5.1.2 for a description of the register naming
convention.
PORT61: AT Compatibility Register
Fixed IO space; offset: 61h. Default: 00h.
7
SERR
TMR2EN. Programmable interval timer, timer number 2 enable. Read-write. 1=PIT timer 2 is enabled to count.
0=PIT timer 2 is halted.
SPKREN. Speaker enable. Read-write. 1=The output of PIT timer number 2 drives the SPKR pin. 0=SPKR is held
low.
CLRSERR. Clear PORT61[SERR]. Read-write. 1=Bit[7] of this register, SERR, is asynchronously cleared.
0=PORT61[SERR] may be set high.
CLRIOCHK. Clear PORT61[IOCHK]. Read-write. 1=Bit[6] of this register, IOCHK, is asynchronously cleared.
0=PORT61[IOCHK] may be set high.
RSHCLK. Refresh clock. Read only. This bit toggles state at intervals specified by PIT timer 1 (normally, every 15
microseconds).
TMR2. Programmable interval timer, timer number 2 output. Read only. This bit provides the current state of the
output signal from legacy PIT timer number 2.
IOCHK. IOCHK# latch. Read only. This bit is set high when the IOCHK# pin is asserted or if there is a sync-
with-error message received on the LPC bus; it stays high until cleared by PORT61[CLRIOCHK]. The state of this
bit is combined with RTC70[NMIDIS] and PORT61[SERR] to generate NMI interrupts.
SERR. SERR# latch. Read only. This bit is set high when SERR# is asserted and stays high until cleared by
PORT61[CLRSERR]. The state of this bit is combined with RTC70[NMIDIS] and PORT61[IOCHK] to generate
NMI interrupts.
PORT92: System Control Register
Fixed IO space; offset: 92h. Default: 00h.
7
Reserved
RSTCPU. Generate processor reset pulse. Read-write. When this bit is low and then written to a high, the IC
generates a 1.0 to 1.5 microsecond pulse to either CPURST# or INIT#, based on the state of C0A47[CPURS]. This
bit must be written to a low again before another processor reset can be generated. Note: Use of this bit is enabled by
C0A41[P92FR].
A20EN. Processor address bit 20 enable. Write only; reads provide the current state of the A20M# pin rather than
the state of the bit. The value written to this bit is ORed with the KA20G bit from the keyboard controller and then
routed to the A20M# pin. In order for this bit to control A20M#, KA20G must be low.
Legacy Registers
Miscellaneous Legacy and Fixed IO Address Registers
6
IOCHK
6
Reserved
5
TMR2
5
Reserved
4
RSHCLK
4
Reserved
Preliminary Information
3
CLRIOCHK CLRSERR
3
Reserved
AMD-766
2
2
Reserved
TM
Peripheral Bus Controller Data Sheet
1
SPKREN
1
A20EN
0
TMR2EN
0
RSTCPU
42