AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 30

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
4.6.4
The IC supports three PNP IRQs and two PNP chip selects. The registers that specify these are C3A44 and C3A46.
The PNP pins are multiplexed with other functions. The control registers that specify the functions (the GPIO
control registers PM[D3:C0], PM[FF:F4]) must be set up appropriately for the PNP functions to operate.
4.6.5
The general-purpose IO pins, GPIO[31:0], may be assigned to be inputs, outputs, interrupt generators, or bus
controls. These pins may be programmed to be general-purpose IO or to serve alternate functions; see the PM[FF:F4,
D3:C0] register definitions. Many of these pins are named after their alternate functions. There is one control
register for each pin, PM[FF:F4, D3:C0]. IRQ status and enables are available for each pin in registers PMD4 and
PMD8.
General-purpose IO functions. When programmed as a GPIO pin, the following functions are available:
The following diagram shows the format for all GPIO pins. The input path is not disabled when the output path is
enabled or when the pin is used for an alternate function. In order for the latch to be set, the LE input must go high.
Debounce. The input signal must be active and stable for 12 to 16 milliseconds before the output signal is asserted.
GPIO output clocks. There are two GPIO output clocks (numbered 0 and 1). They are specified by PMDC. Each
output clock includes a 7-bit programmable high time, a 7-bit programmable low time, and the counter may be
clocked by one of four frequencies. Here are the options:
The output of the two GPIO output clocks may be selected to drive the output of any of the GPIO pins. They may be
used to blink LEDs or for other functions.
PMDC[CLK[1,0]BASE]
To interrupt generator or
Outputs.
-
-
Inputs.
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-
-
-
Plug And Play
General Purpose IO
May be set high or low.
May be controlled by GPIO output clocks 0 or 1 (see PMDC).
Active high or active low programmable.
SCI or SMI IRQ capable.
May be latched or not latched.
Inputs may be debounce protected.
alternative logic
LTCH_STS
00b
01b
10b
11b
LATCH
Output path
Input path
1
0
250 microseconds
Base clock period
128 milliseconds
16 milliseconds
2 milliseconds
Q
Latch
Preliminary Information
LE
D
Output high time range
250 s to 32 ms
2 ms to 256 ms
16 ms to 2 seconds
128 ms to 16.4 seconds
Vcc
clocks 0 and 1
1
0
GPIO output
DEBOUNCE
flip-flop
Output
AMD-766
Debounce
Circuit
TM
Peripheral Bus Controller Data Sheet
1
0
ACTIVEHI
Output low time range
250 us to 32 ms
2 ms to 256 ms
16 ms to 2 seconds
128 ms to 16.4 seconds
RTIN
Output
mode
Pad
30