PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 10

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

2.0 Functional Description
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the RX__FIFO. In fact, a frame will be lost in 8237 mode when the ST__FIFO is full for the entire time during which the frame is
being received, even though there were empty locations in the RX__FIFO. This is because no data bytes can be loaded into the
RX__FIFO and then transferred to memory by the DMA controller, unless there is at least one available entry in the ST__FIFO
to store the number of received bytes. This information, as mentioned before, is needed by the software to locate the frame
boundaries in the DMA memory buffer.
In the event that a number of frames are lost, for any of the reasons mentioned above, one or more lost-frame indications includ-
ing the number of lost frames, are loaded into the ST__FIFO.
Frames can also be lost in PIO mode, but only when the RX__FIFO is full. The reason being that, in these cases, the ST__FIFO
is only used to store lost-frame indications. It will not store frame status and byte count.
2.6 CONSUMER ELECTRONICS IR (CEIR) MODE
The Consumer Electronics IR circuitry is designed to optimally support all the major protocols presently used in remote-controlled
home entertainment equipment. The main protocols currently in use are: RC-5, RC-6, RECS 80, NEC and RCA. The PC87108,
in conjunction with an external optical module, provides the physical layer functions necessary to support these protocols. These
functions include modulation, demodulation, serialization, de-serialization, data buffering, status reporting, interrupt generation,
etc. The software is responsible for the generation of the infrared code to be transmitted, and for the interpretation of the received
code.
2.6.1 CEIR Transmit Operation
The code to be transmitted consists of a sequence of bytes that represent either a bit string or a set of run-length codes. The num-
ber of bits or run-length codes usually needed to represent each infrared code bit depends on the infrared protocol used. The
RC-5 protocol, for example, needs two bits or between one and two run-length codes to represent each infrared code bit.
CEIR transmission starts when the transmitter is empty and either the CPU or the DMA controller writes code bytes into the
TX__FIFO. The transmission is normally completed when the CPU sets the S__EOT bit in the ASCR register before writing the
last byte, or when the DMA controller activates the TC signal. Transmission is also completed if the CPU simply stops transferring
data and the transmitter becomes empty. In this case however, a transmitter underrun condition will be generated. The underrun
must be cleared before the next transmission can occur. The code bytes written into the TX__FIFO are either de-serialized or
run-length decoded, and the resulting bit string is modulated by a subcarrier signal and sent to the transmitter LED. The bit rate
of this bit string, like in the UART mode, is determined by the value programmed in the baud generator divisor register. Unlike a
UART transmission, start, stop and parity bits are not included in the transmitted data stream. A logic 1 in the bit string will keep
the LED off, so no infrared signal is transmitted. A logic 0 will generate a sequence of modulating pulses which will turn on the
transmitter LED. Frequency and pulse width of the modulating pulses are programmed by the MCFR and MCPW bits in the
IRTXMC register as well as the TXHSC bit in the RCCFG register.
The RC__MMD bits select the transmitter modulation mode. If C__PLS mode is selected, modulation pulses are generated con-
tinuously for the entire time in which one or more logic 0 bits are being transmitted. If 6__PLS or 8__PLS modes are selected,
6 or 8 pulses are generated each time one or more logic 0 bits are transmitted following a logic 1 bit. C__PLS modulation mode
is used for RC-5, RC-6, NEC and RCA protocols. 8__PLS or 6__PLS modulation mode is used for the RECS 80 protocol. The
8__PLS or 6__PLS mode allows minimization of the number of bits needed to represent the RECS 80 infrared code sequence.
The current transmitter implementation supports only the modulated modes of the RECS 80 protocol. The flash mode is not sup-
ported since it is not popular and is becoming less frequently used.
Note: The total transmission time for the logic 0 bits must be equal or greater than 6 or 8 times the period of the modulation subcarrier, otherwise fewer pulses will
be transmitted.
2.6.2 CEIR Receive Operation
The CEIR receiver is significantly different from a UART receiver for two basic reasons. First, the incoming infrared signals are
DASK modulated. Therefore, a demodulation operation may be necessary. Second, there are no start bits in the incoming data
stream.
Whenever an infrared signal is detected, the operations performed by the receiver are slightly different depending on whether or
not receiver demodulation is enabled. If the demodulator is not enabled, the receiver will immediately switch to the active state.
If the demodulator is enabled, the receiver checks the subcarrier frequency of the incoming signal, and it switches to the active
state only if the frequency falls within the programmed range. If this is not the case, the signal is ignored and no other action is
taken.
When the receiver active state is entered, the RXACT bit in the ASCR register is set to 1. Once in the active state, the receiver
keeps sampling the infrared input signal and generates a bit stream where a logic 1 indicates an idle condition and a logic 0 in-
dicates the presence of infrared energy. The infrared input is sampled regardless of the presence of infrared pulses at a rate de-
termined by the value loaded into the baud generator divisor register. The received bit string is either de-serialized and assembled
into 8-bit characters, or it is converted to run-length encoding values. The resulting data bytes are then transferred to the
RX__FIFO.
The receiver also sets the RXWDG bit in the ASCR register each time an infrared pulse signal is detected. This bit is automatically
cleared when the ASCR register is read, and it is intended to assist the software in determining when the infrared link has been
idle for a certain time. The software can then stop the data reception by writing a 1 into the RXACT bit to clear it and return the
receiver to the inactive state.
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