PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 18

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
B7–6 RXFTH [1–0] – RX__FIFO Interrupt Threshold.
3.1.4 LCR/BSR – Link Control/Bank Select Register
These registers share the same address.
The Link Control Register (LCR) is used to select the communications format for data transfers in UART, Sharp-IR and SIR
modes.
The Bank select register (BSR) is used to select the register bank to be accessed next.
When the CPU performs a read cycle from this address location, the BSR content is returned. The content of LCR is returned
when the CPU reads the SH__LCR register in bank 3.
During CPU write cycles, the setting of bit 7 (BKSE, bank select enable) determines the register to be accessed.
If bit 7 is 0, both LCR and BSR are written into. If bit 7 is 1, only BSR is written into, and LCR is not affected. This prevents the
communications format from being spuriously affected when a bank other than bank 0 is accessed. Upon reset, all bits are set
to 0.
LCR – Link Control Register
The Format of LCR is shown in Figure 9 .
Bits 0 to 6 are only effective in UART, Sharp-IR and SIR modes.
They are ignored in MIR, FIR and CEIR modes.
B1–0 WLS [1–0] – Character Length.
B2
B3
B4
Bits
Function
Reset State
An interrupt is generated when the TX__FIFO level drops below the threshold.
These bits select the RX__FIFO interrupt threshold level.
An interrupt is generated when the RX__FIFO level is equal to or above the threshold.
These bits specify the length of each transmitted or received serial character.
STB – Stop Bits.
Number of stop bits in each transmitted serial character. If this bit is 0, 1 stop bit is generated in the transmitted data. If
it is 1 and a 5-bit character length is selected via bits 0 and 1, 1.5 stop bits are generated. If it is 1 and a 6, 7 or 8-bit char-
acter length is selected, 2 stop bits are generated. The receiver checks 1 stop bit only, regardless of the number of stop
bits selected.
PEN – Parity Enable.
When set to 1, parity bits are generated and checked by the transmitter and receiver channels respectively.
EPS – Even Parity.
BKSE
B7
0
Bits 5–4
Bits 7–6
00
01
10
11
00
01
10
11
SBRK
B6
Bits 10
0
00
01
10
11
FIGURE 9. Link Control Register
(Continued)
RX__FIFO Thresh.
TX__FIFO Thresh.
STKP
B5
(16 Levels)
(16 Levels)
0
13
14
1
3
9
1
4
8
18
EPS
B4
0
Character Length
5 Bits
6 Bits
7 Bits
8 Bits
RX__FIFO Thresh.
TX__FIFO Thresh.
PEN
B3
0
(32 Levels)
(32 Levels)
17
25
16
26
1
7
1
8
STB
B2
0
WLS1
B1
0
WLS0
B0
0