PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 16

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
Extended Mode
The EIR register does not return an encoded value like in the non-extended mode. Each bit represents an event flag and is set
to 1 when the corresponding event occurred or is pending, regardless of the setting of the corresponding bit in the IER register.
Bit 4 is cleared when this register is read if an 8237 type DMA controller is used. All other bits are cleared when the corresponding
interrupts are acknowledged.
B0 RXHDL__EV – Receiver High-Data-Level Event.
B1 TXLDL__EV – Transmitter Low-Data-Level Event.
B2 UART, Sharp-IR, SIR Modes
Note: A high speed CPU can service the interrupt generated by the last frame byte reaching the RX_FIFO bottom before that byte is transferred to memory by the
Bits
Function
Reset State
EIR Bits
3210
0001
0110
0100
1100
0010
0000
FIFOs Disabled: Set to 1 when one character is in the receiver holding register.
FIFOs Enabled: Set to 1 when the RX__FIFO level is equal to or above the threshold level, or an RX__FIFO time-out has
occurred.
FIFOs Disabled: Set to 1 when the transmitter holding register is empty.
FIFOs Enabled: Set to 1 when the TX__FIFO level is below the threshold level.
LS__EV – Link Status Event.
Set to 1 when a receiver error or break condition is reported.
Note that, when the FIFOs are enabled, the PE, FE and BRK conditions are only reported when the associated character
reaches the bottom of the RX__FIFO. An overrun error (OE) is reported as soon as it occurs.
MIR, FIR Modes
LS__EV/TXHLT__EV – Link Status/Transmitter Halted Event.
Set to 1 when any of the following conditions occur:
1. Last byte of received frame reaches the bottom of the RX__FIFO
2. Receiver overrun
3. Transmitter underrun
4. Transmitted halted on frame end
CEIR Mode
LS__EV/TXHLT__EV – Link Status/Transmitter Halted.
Set to 1 when a receiver overrun or a transmitter underrun condition occurs.
DMA controller. This can happen when the CPU interrupt latency is shorter than the RX_FIFO time-out (Refer to the “FIFO Time-out” section). A DMA request
is generated only when the RX_FIFO level reaches the DMA threshold or when a FIFO time-out occurs, in order to minimize the performance degradation due
Priority
Highest
Second
Second
Fourth
Level
Third
N/A
TMR__EV SFIF__EV TXEMP__EV/
B7
0
None
Link Status
Receiver
High-Data-
Level Event
RX__FIFO
Timeout
Transmitter
Low-Data-
Level Event
Modem
Status
Interrupt
Type
B6
0
FIGURE 7. Event Identification Register, Extended Mode
TABLE 3. Non-Extended Mode Interrupt Priorities
None
Parity error, or Framing error, or Data
overrun, or Break event
Receiver holding register full, or
RX__FIFO level equal to or above
threshold
At least 1 character in RX__FIFO, and
no character input to or read from the
RX__FIFO for 4 character times
Transmitter holding register or TX__FIFO
empty
Any transition on CTS , DSR , or DCD ,
or low-to-high transition on RI
PLD__EV
B5
1
(Continued)
Interrupt Source
DMA__EV MS__EV
B4
0
16
B3
0
TXHLT__EV
LS__EV/
N/A
Reading the LSR Register
Reading the RXD port, or RX__FIFO
level drops below threshold
Reading the RXD port
Reading the EIR register if this interrupt
is currently the highest priority pending
interrupt, or writing into the TXD port
Reading the MSR register
B2
0
Interrupt Reset Control
TXLDL__EV RXHDL__EV
B1
1
B0
0