PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 35

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
3.7.1 IRCR3 – Infrared Control Register 3
Used to select the operating mode of the infrared interface.
Upon reset, the content of this register is 20h.
B0 Reserved.
B1 TXCRC__DS – Disable Transmitter CRC.
B2 TXCRC__INV – Invert Transmitter CRC.
B3 Reserved.
B4 MIR__CRC – MIR Mode CRC Select.
B5 FIR__CRC – FIR Mode CRC Select.
B6 SHMD__DS – Sharp-IR Modulation Disable.
B7 SHDM__DS – Sharp-IR Demodulation Disable.
3.7.2 MIR__PW – MIR Pulse Width Register
This register is used to program the width of the transmitted MIR infrared pulses in increments of either 20.833 ns or 41.666 ns
depending on the setting of the MDSR bit in the IRCR2 register. The programmed value has no effect on the MIR receiver. After
reset, the content of this register is 0Ah.
B3-0 MPW [3–0] – MIR Signal Pulse Width
Reset State
Function
Reset State
Write 0.
When set to 1, a CRC is not transmitted.
When set to 1, an inverted CRC is transmitted. This bit can be used to force a bad CRC for testing purposes.
Write 0.
Determines the length of the CRC in MIR mode.
0
1
Determines the length of the CRC in FIR mode.
0
1
When set to 1, internal 500 kHz transmitter modulation is disabled.
When set to 1, internal 500 kHz receiver demodulation is disabled.
Function
Bits
Bits
16-bit CRC
32-bit CRC
16-bit CRC
32-bit CRC
SHDM__DS
B7
0
res
B7
0
00XX
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Encoding
SHMD__DS
res
B6
B6
0
0
FIGURE 24. Infrared Control Register 3
FIGURE 25. MIR Pulse Width Register
Reserved
83.33 ns
104.16 ns
125 ns
145.83 ns
166.66 ns
187.50 ns
208.33 ns
229.16 ns
250 ns
270.83 ns
Pulse Width, MDRS = 0
FIR__CRC
(Continued)
res
B5
0
B5
1
35
MIR__CRC
B4
res
0
B4
0
Reserved
166.66 ns
208.33 ns
250 ns
291.66 ns
333.33 ns
374.99 ns
416.66 ns
458.33 ns
500 ns
541.66 ns
Pulse Width, MDRS = 1
MPW3
B3
1
res
B3
0
TXCRC__INV TXCRC__DS
MPW2
B2
0
B2
0
MPW1
B1
1
B1
0
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MPW0
B0
0
res
B0
0