PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 29

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
B3–2 RF__SIZ [1–0] – RX__FIFO Levels Select.
B5–4 PRESL [1–0] – Prescaler Select.
B6
B7
3.3.5 TXFLV – TX__FIFO Level, Read-Only
This register returns the number of bytes in the TX__FIFO. It can be used for software debugging, or during recovery from a trans-
mitter underrun condition in one of the high-speed infrared modes.
B5–0 TFL [5–0] – Number of bytes in TX__FIFO.
B7–6 Reserved.
3.3.6 RXFLV – RX__FIFO Level, Read-Only
This register returns the number of bytes in the RX__FIFO. It can be used for software debugging.
B5–0 RFL [5–0] – Number of bytes in RX__FIFO.
B7–6 Reserved.
Bits
Function
Reset State
Bits
Function
Reset State
These bits select the number of levels for the RX__FIFO.
They are effective only when the FIFOs are enabled.
The prescaler divides the 24 MHz input clock frequency to provide the clock for the baud generator.
Reserved.
Read/write 0.
LOCK – Lock Bit.
When set to 1, accesses to the baud generator divisor register through LBGD(L) and LBGD(H) as well as fallback are dis-
abled from non-extended mode.
In this case two scratchpad registers overlayed with LBGD(L) and LBGD(H) are enabled, and any attempted CPU access
of the baud generator divisor register through LBGD(L) and LBGD(H) will access the scratchpad registers instead. This
bit must be set to 0 when extended mode is selected.
Return 0’s.
Return 0’s.
Note: The contents of TXFLV and RXFLV are not frozen during CPU reads. Therefore, invalid data could be returned if the CPU reads these registers dur-
ing normal transmitter and receiver operation. To obtain correct data, the software should perform three consecutive reads and then take the data
from the second read, if first and second read yield the same result, or from the third read, if first and second read yield different results.
res
res
B7
B7
0
0
res
res
B6
B6
0
0
Bits 5–4
Bits 3–2
0 0
0 1
1 0
1 1
00
01
1x
FIGURE 18. Transmit FIFO Level
FIGURE 19. Receive FIFO Level
RFL5
TFL5
(Continued)
B5
B5
0
0
29
RFL4
TFL4
B4
B4
0
0
RX__FIFO Levels
Prescaler Value
Reserved
Reserved
1.625
TFL3
RFL3
13.0
1.0
B3
B3
16
32
0
0
TFL2
RFL2
B2
B2
0
0
TFL1
RFL1
B1
B1
0
0
www.national.com
TFL0
RFL0
B0
B0
0
0