PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 12

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

2.0 Functional Description
(Continued)
now writes data into the TX__FIFO, the transmitter will not start sending the data until the TX__FIFO level reaches either 14 for
a 16-level TX__FIFO, or 30 for a 32-level TX__FIFO, at which time the internal flag is cleared. The internal flag is also cleared
and the transmitter starts transmitting when a time-out condition is reached. This prevents some bytes from being in the
TX__FIFO indefinitely if the threshold is not reached.
The time-out mechanism is implemented by a timer that is enabled when the internal flag is set and there is at least one byte in
the TX__FIFO. Whenever a byte is loaded into the TX__FIFO the timer gets reloaded with the initial value. If no bytes are loaded
for a 64-µs time, the timer times out and the internal flag gets cleared, thus enabling the transmitter.
2.9 AUTOMATIC FALLBACK TO 16550 COMPATIBILITY MODE
This feature is designed to support existing legacy software packages using the 16550 UART.
For proper operation, many of these software packages require that the device look identical to a plain 16550 since they access
the UART registers directly.
Due to the fact that several extended features as well as new operational modes are provided, the user must make sure that the
device is in the proper state before a legacy program can be executed.
The fallback mechanism is designed for this purpose. It eliminates the need for user intervention to change the state of the device,
when a legacy program must be executed following completion of a program that used any of the device’s extended features.
This mechanism automatically switches the device to 16550 compatibility mode and turns off any extended features whenever the
baud generator divisor register is accessed through the LBGD(L) or LBGD(H) ports in register bank 1.
In order to avoid spurious fallbacks, baud generator divisor ports are provided in bank 2. Accesses of the baud generator divisor
through these ports will change the baud rate setting but will not cause a fall back.
New programs, designed to take advantage of the extended features, should not use LBGD(L) and LBGD(H) to change the baud
rate. They should use BGD(L) and BGD(H) instead.
A fallback can occur from either extended or non-extended modes. If extended mode is selected, fallback is always enabled. In
this case, when a fallback occurs, the following happens:
1. Transmitter and receiver FIFOs will switch to 16 levels.
2. A value of 13 will be selected for the baud generator prescaler.
3. The ETDLBK and BTEST bits in the EXCR1 Register will be cleared.
4. UART mode will be selected.
5. A switch to non-extended mode will occur.
When a fallback occurs from non-extended mode, only the first three of the above actions will take place. No switching to UART
mode occurs if either Sharp__IR or SIR infrared modes were selected. This prevents spurious switchings to UART mode when
a legacy program, running in infrared mode, accesses the baud generator divisor register from bank 1.
Fallback from non-extended mode can be disabled by setting the LOCK bit in the EXCR2 register. When Lock is set to 1 and the
device is in non-extended mode, two scratchpad registers overlayed with LBGD(L) and LBGD(H) are enabled. Any attempted
CPU access of the baud generator divisor register through LBGD(L) and LBGD(H) will access the scratchpad registers, and the
baud rate setting will not be affected. This feature allows existing legacy programs to run faster than 115.2 kbaud without their be-
ing aware of it.
2.10 PIPELINING
This feature is designed to support the IrDA infrared modes and it allows minimization of the time delay from the end of a nego-
tiation phase to the subsequent data transfer phase.
The device accomplishes this objective by automatically selecting a new mode and/or loading new values into the baud generator
divisor register as soon as the current data transmission completes and the transmitter becomes empty. The new operational
mode and the baud divisor value are programmed into special pipeline registers.
Pipelining is automatically disabled after a pipeline operation takes place. It should be re-enabled by the software after the special
pipeline registers have been reloaded.
Even though there are no other restrictions between source and target modes, aside from having to be IrDA modes, pipelining
will most likely be used from SIR as the source mode, since SIR is the mode used by the negotiation procedures in the presently
defined IrDA protocols.
Following a pipeline operation, the transmitter will be halted for 250 µs to allow the newly selected receive filter in the remote op-
tical transceiver to stabilize. If a switch from either MIR or FIR to SIR occurred as a result of pipelining, the transmitter will be
halted for 250 µs or a character time (at the newly selected baud rate), whichever is greater. This is to guarantee that reception
at a remote station of any character triggered by an interaction pulse is complete before the next SIR data transmission begins.
Since a pipelining operation is performed without software intervention, automatic transceiver configuration must be enabled.
2.11 OPTICAL TRANSCEIVER INTERFACE
The PC87108A implements a very flexible interface for the external infrared transceiver. Several signals are provided for this pur-
pose. A transceiver module with one or two receive signals, or two transceiver modules can be directly interfaced without any ad-
ditional logic.
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