PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 20

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
Non-Extended Mode
The format of the non-extended mode MCR is shown in Figure 10 .
B0
B1
B2
B3
B4
B7–5 Reserved.
Extended Mode
The format of the extended mode MCR is shown in Figure 11 .
Note: Bits 2 to 7 should always be initialized after the operational mode is changed from non-extended to extended.
B0
B1
B2
B3
Bits
Function
Reset State
Bits
Function
Reset State
DTR – Data Terminal Ready.
This bit controls the DTR signal output.
When it is set to 1, DTR is driven low.
In loopback mode this bit internally drives DSR.
RTS – Request to Send.
This bit controls the RTS signal output.
When it is set to 1, RTS is driven low.
In loopback mode this bit internally drives CTS.
RILP – Loopback RI.
In normal operation this bit is unused.
In loopback mode this bit internally drives RI.
ISEN/DCDL – Interrupt Signal Enable/Loopback DCD.
In normal operation this bit controls the interrupt signal, and it must be set to 1 in order to enable it.
In loopback mode, this bit internally drives DCD, and the interrupt signal is always enabled.
Note: New programs should always keep this bit set to 1 during normal operation. The interrupt signal should be controlled through the Plug-n-Play logic.
LOOP – Loopback Enable.
When set to 1, loopback mode is selected.
This bit accesses the same internal register as bit 4 of the EXCR1 register.
Refer to the section describing the EXCR1 register for more information on the loopback mode.
Forced to 0.
DTR – Data Terminal Ready.
This bit controls the DTR signal output.
When it is set to 1, DTR is driven low.
In loopback mode this bit internally drives both DSR and RI.
RTS – Request to Send.
This bit controls the RTS signal output.
When it is set to 1, RTS is driven low.
In loopback mode this bit internally drives both CTS and DCD.
DMA__EN – DMA Mode Enable.
When set to 1, DMA mode of operation is enabled.
When data transfers are performed by a DMA controller, the transmit and/or receive data interrupts should be disabled to
avoid spurious interrupts.
Note that DMA cycles always access the data holding registers or FIFOs, regardless of the selected bank.
TX__DFR – Transmit Deferral.
MDSL2
B7
B7
—
0
0
FIGURE 10. Modem Control Register, Non-Extended Mode
FIGURE 11. Modem Control Register, Extended Mode
MDSL1
B6
—
0
B6
0
B5
—
0
MDSL0
(Continued)
B5
0
LOOP
B4
0
IR__PLS
20
B4
0
DCDLP
ISEN/
TX__DFR
B3
0
B3
0
DMA__EN
RILP
B2
B2
0
0
RTS
RTS
B1
B1
0
0
DTR
B0
DTR
0
B0
0