PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 23

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
B5 TXRDY – Transmitter Ready.
B6 TXEMP – Transmitter Empty.
B7 UART, Sharp-IR, SIR Modes
3.1.7 MSR – Modem Status Register
The function of this register depends on the selected operational mode. When UART Mode is selected, this register provides the
current-state as well as state-change information of the status lines from the MODEM or Data Set. When any one of the Infrared
Modes is selected, the register function is controlled by the setting of the IRMSSL bit in the IRCR2 register. If IRMSSL is 0, the
MSR register works the same as in UART mode. If IRMSSL is 1, the MSR register returns the value 30h, regardless of the state
of the MODEM input lines.
In Loopback mode, the MSR register works similarly except that its status inputs are internally driven by appropriate bits in the
MCR register since the MODEM input lines are internally disconnected. Refer to the sections describing the MCR and EXCR1
register for more information.
A description of the various bits of MSR, with Loopback disabled and UART Mode selected, is provided below. When any of the
bits 0 to 3 is set to 1, a Modem Status Interrupt is generated. Bits 0 to 3 are set to 0 when any of the following events occurs.
1. Hardware reset.
2. The MSR register is read.
3. The operational mode is changed and the IRMSSL bit is 0.
Note: The modem status lines have no effect on transmitter and receiver operation. They can be used as general purpose inputs.
B0 DCTS – Delta Clear to Send.
B1 DDSR – Delta Data Set Ready.
B2 TERI – Ring Indicator Trailing Edge.
B3 DDCD – Delta Data Carrier Detect.
B4 CTS – Clear to Send.
B5 DSR – Data Set Ready.
B6 RI – Ring Indicator.
Bits
Function
Reset State
Cleared upon read.
This bit is set to 1 when the Transmitter Holding Register or the TX__FIFO is empty.
It is cleared when a data character is written to the TXD port.
Set to 1 when the Transmitter is empty. The transmitter empty condition occurs when the Holding Register or the TX__FIFO
is empty, and the transmitter front-end is idle.
ER__INF – Error in RX__FIFO.
Set to 1 when at least one character with a PE, FE or BRK condition is in the RX__FIFO.
This bit is always 0 in 16450 mode.
MIR, FIR Modes
FR__END – Frame End.
Set to 1 when the last byte (Frame End Byte) of a received frame reaches the bottom of the RX__FIFO.
Cleared upon read.
Set to 1 when the CTS input changes state.
Cleared upon read.
Set to 1 when the DSR input changes state.
Cleared upon read.
Set to 1 when the RI input changes from a low state to a high state.
Cleared upon read.
Set to 1 when the DCD input changes state.
Cleared upon read.
This bit returns the complement of the CTS input.
This bit returns the complement of the DSR input.
This bit returns the complement of the RI input.
DCD
B7
X
B6
RI
X
FIGURE 13. Modem Status Register
DSR
(Continued)
B5
X
CTS
23
B4
X
DDCD
B3
0
TERI
B2
0
DDSR
B1
0
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DCTS
B0
0