PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 30

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
3.4 BANK 3
3.4.1 MID – Module Identification Register, Read Only
When read, it returns the module revision.
The returned value is 2Xh.
3.4.2 SH__LCR – Link Control Register Shadow, Read Only
This register returns the value of the LCR register.
The LCR register is written into when a byte value with bit 7 set to 0 is written to the LCR/BSR registers location (at offset 3) from
any bank.
3.4.3 SH__FCR – FIFO Control Register Shadow, Read-Only
This register returns the value written into the FCR register in bank 0.
3.4.4 LCR/BSR – Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.5 BANK 4
3.5.1 TMR – Timer Register
This register is used to program the reload value for the internal down-counter as well as to read the current counter value. TMR
is 12 bits wide and is split into two independently accessible parts occupying consecutive address locations. TMR(L) is located
at the lower address and accesses the least significant 8 bits, whereas TMR(H) is located at the higher address and accesses
the most significant 4 bits. Values from 1 to 2
4 bits of TMR(H) are reserved and must be written with 0’s. The timer resolution is 125 µs, providing a maximum time-out interval
of approximately 0.5 seconds. To properly program the timer, the CPU must always write the lower value into TMR(L) first, and
then the upper value into TMR(H). Writing into TMR(H) causes the counter to be loaded. A read of TMR returns the current
counter value if the CTEST bit is 0, or the programmed reload value if CTEST is 1. In order for a read access to return an accurate
value, the CPU should always read TMR(L) first, and then TMR(H). This is because a read of TMR(H) returns the content of an
internal latch that is loaded with the 4 most significant bits of the current counter value when TMR(L) is read. After reset, the con-
tent of this register is indeterminate.
Address
Address
Offset
Offset
4–7
0
1
2
3
4
5
6
7
0
1
2
3
TMR(L)
TMR(H)
IRCR1
LCR/BSR
TFRL(L)/
TFRCC(L)
TFRL(H)/
TFRCC(H)
RFRML(L)/
RFRCC(L)
RFRML(H)/
RFRCC(H)
MID
SH__LCR
SH__FCR
LCR/BSR
Reserved
Register
Register
12
Name
Name
TABLE 10. Bank 4 Register Set
TABLE 9. Bank 3 Register Set
− 1 can be used. The zero value is reserved and must not be used. The upper
(Continued)
Module Identification Register
Link Control Register Shadow
FIFO Control Register Shadow
Link Control/Bank Select Registers
Timer Register (Low-Byte)
Timer Register (High-Byte)
Infrared Control Register 1
Link Control/Bank Select Registers
Transmitter Frame Length/
Current Count (Low Byte)
Transmitter Frame Length/
Current Count (High Byte)
Receive Frame Maximum Length/
Current Count (Low Byte)
Receive Frame Maximum Length/
Current Count (High Byte)
30
Description
Description