PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 42

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
3.8.5.2 IRCFG2 – Infrared Interface Configuration Register 2
This register holds the transceiver configuration data for MIR and FIR Modes.
B2–0 MIRC [2–0] – MIR Mode Transceiver Configuration.
B3
B6–4 FIRC [2–0] – FIR Mode Transceiver Configuration.
B7
3.8.5.3 IRCFG3 — Infrared Interface Configuration 3
This register holds the transceiver configuration data for Low-Speed and High-Speed Consumer-IR Modes.
B2–0 RCLC [2–0] – Consumer-IR Mode Transceiver Configuration, Low-Speed.
B3
B6–4 RCHC [2–0] – Consumer-IR Mode Transceiver Configuration, High-Speed.
B7
3.8.5.4 IRCFG4 – Infrared Interface Configuration 4
This register is used to configure the receiver data path and enable the automatic selection of the configuration pins. After reset,
the content of this register is 0.
B2–0 Reserved.
Reset State
Reset State
Reset State
Function
Function
Function
Bits
These bits will drive the ID/IRSL[2–0] pins when AMCFG is 1 and MIR Mode is selected.
They are unused when AMCFG is 0 or when the ID/IRSL [2–0] pins are programmed as inputs.
Upon read, these bits return the values previously written.
Reserved.
Write 0.
These bits will drive the ID/IRSL [2–0] pins when AMCFG is 1 and FIR Mode is selected.
They are unused when AMCFG is 0 or when the ID/IRSL [2–0] pins are programmed as inputs.
Upon read, these bits return the values previously written.
Reserved.
Write 0.
These bits will drive the ID/IRSL[2–0] pins when AMCFG is 1 and Consumer-IR Mode with 30 kHz–56 kHz receiver sub-
carrier frequency is selected.
They are unused when AMCFG is 0 or when the ID/IRSL[2–0] pins are programmed as inputs.
Upon read, these bits return the values previously written.
Reserved.
Write 0.
These bits will drive the ID/IRSL[2–0] pins when AMCFG is 1 and Consumer-IR Mode with 400 kHz–480 kHz receiver
subcarrier frequency is selected.
They are unused when AMCFG is 0 or when the ID/IRSL[2–0] pins are programmed as inputs.
Upon read, these bits return the values previously written.
Reserved.
Write 0.
Bits
Bits
AMCFG
B7
res
res
B7
B7
0
0
0
IRRX__MD
RHCH2
FIRC2
B6
B6
0
0
B6
0
FIGURE 32. Infrared Configuration Register 2
FIGURE 33. Infrared Configuration Register 3
FIGURE 34. Infrared Configuration Register 4
RHCH1
FIRC1
(Continued)
IRSL0__DS
B5
B5
0
0
B5
0
42
RHCH0
FIRC0
B4
B4
0
0
RXINV
B4
0
res
res
B3
B3
0
0
IRSL21__DS
B3
0
RCLC2
MIRC2
B2
B2
0
0
res
B2
0
RCLC1
MIRC1
B1
B1
0
0
res
B1
0
RCLC0
MIRC0
B0
B0
0
0
res
B0
0