PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 33

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
3.6.4 IRCR2 – Infrared Control Register 2
Upon reset, the content of this register is 02h.
B0 IR__FDPLX – Infrared Full Duplex Mode.
B1 IRMSSL – MSR Register Function Select in Infrared Mode.
B2 MDRS – MIR Data Rate Select.
B3 TX__MS – Transmitter Mode Select.
B4 AUX__IRRX – Auxiliary Infrared Input Select.
B5 FEND__MD – Frame End Control.
B6 SFTSL – ST__FIFO Threshold Select.
B7 Reserved.
3.6.5 ST__FIFO – Status FIFO
The ST__FIFO is used in MIR and FIR Modes.
It is an 8-level FIFO and is intended to support back-to-back incoming frames in DMA mode, when an 8237-type DMA controller
is used. Each ST__FIFO entry contains either status information and frame length for a single frame, or the number of lost frames.
The bottom entry spans three address locations, and is accessed via the FRM__ST, RFRL(L)/LSTFRC and RFRL(H) registers.
The ST__FIFO is flushed when a hardware reset occurs or when the receiver is soft reset.
Note: The status and length information of received frames is loaded into the ST__FIFO whenever the DMA__EN bit in the extended-mode MCR register is set to
Bits
Function
Reset State
When set to 1, the infrared receiver is not masked during transmission.
This bit selects the behavior of the modem status register/interrupt when any infrared mode is selected. When UART mode
is selected, the modem status register and interrupt function normally, and this bit is ignored.
0
1
This bit determines the data rate in MIR mode.
0
1
This bit is used in MIR and FIR modes only. When it is set to 1, transmitter frame-end stop mode is selected. In this case the
transmitter stops after transmission of a frame is complete, if the end-of-frame condition was generated by the TFRCC
counter reaching 0. The transmitter can be restarted by clearing the TXHFE bit in the ASCR register.
When set to 1, the infrared signal is received from the auxiliary input. See Table 17 .
This bit selects whether a terminal-count condition from the
TFRCC register will generate an EOF in PIO mode or DMA mode.
0
1
An interrupt request is generated when the ST__FIFO level reaches the threshold or when an ST__FIFO time-out occurs.
Read/write 0.
1 and an 8237 type DMA controller is used, regardless of whether the CPU or the DMA controller is transferring the data from the RX__FIFO to memory. This
implies that, during testing, if full duplex is enabled and a DMA channel is servicing the transmitter while the CPU is servicing the receiver, the CPU must still
read the ST__FIFO. Otherwise, it fills up and incoming frames will be rejected.
MSR register and modem status interrupt work as in UART mode.
MSR register returns 30h and the modem status interrupt is disabled.
1.152 Mbps
0.576 Mbps
TFRCC terminal count effective in PIO mode.
TFRCC terminal count effective in DMA mode.
B7
res
0
SFTSL
B6
0
Bit Value
FIGURE 22. Infrared Control Register 2
FEND__MD
0
1
B5
0
(Continued)
AUX__IRRX
33
B4
0
Threshold Level
TX__MS
B3
0
2
4
MDRS
B2
0
IRMSSL
B1
1
IR__FDPLX
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B0
0