PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 34

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
3.6.5.1 FRM__ST – Frame Status Byte at ST__FIFO Bottom, Read-Only
This register returns the status byte at the bottom of the ST__FIFO. If the LOST__FR bit is 0, bits 0 to 4 indicate if any error con-
dition occurred during reception of the corresponding frame. Error conditions will also affect the error flags in the LSR register.
B0 OVR2 – Overrun Error 2.
B1 OVR1 – Overrun Error 1.
B2 BAD__CRC – CRC Error.
B3 PHY__ERR – Physical Layer Error.
B4 MAX__LEN – Maximum Frame Length Exceeded.
B5 Reserved.
B6 LOST__FR – Lost Frame Indicator Flag.
B7 VLD – ST__FIFO Entry Valid.
3.6.5.2 RFRL(L)/LSTFRC – Received Frame Length /Lost-Frame-Count at ST__FIFO Bottom, Read-Only
This register should be read only when the VLD bit in FRM__ST is 1. The information returned depends on the setting of the
LOST__FR bit. Upon reset, all bits are set to 0.
LOST__FR = 0
LOST__FR = 1
3.6.5.3 RFRL(H) – Received-Frame-Length at ST__FIFO Bottom, Read-Only
This register should be read only when the VLD bit in FRM__ST is 1. The information returned depends on the setting of the
LOST__FR bit. Upon reset, all bits are set to 0.
LOST__FR = 0
LOST__FR = 1
Reading this register removes the bottom ST__FIFO entry.
3.7 BANK 6
Bits
Function
Reset State
This bit is set to 1 when incoming characters or entire frames have been discarded due to the ST__FIFO being full.
This bit is set to 1 when incoming characters or entire frames have been discarded due to the RX__FIFO being full.
Set to 1 when a mismatch between the received CRC and the receiver-generated CRC is detected.
Set to 1 when an encoding error or the sequence BOF-data-BOF is detected in FIR mode, or an abort condition is detected
in MIR mode.
Set to 1 when a frame exceeding the maximum length has been received.
Returned data is indeterminate.
Indicates the type of information provided by this ST__FIFO entry.
0
1
When set to 1, the bottom ST__FIFO entry contains valid data.
Entry provides status information and length for a received frame.
Entry provides overrun indications and number of lost frames.
Least significant 8 bits of the received frame length.
Number of lost frames
Most significant 5 bits of the received frame length.
All 0’s
VLD
B7
0
Address
Offset
5–7
0
1
2
3
4
LOST__FR
B6
0
IRCR3
MIR__PW
SIR__PW
LCR/BSR
BFPL
Reserved
Register
Name
TABLE 12. Bank 6 Register Set
FIGURE 23. Frame Status Byte
res.
(Continued)
B5
0
Infrared Control Register 3
MIR Pulse Width Register
SIR Pulse Width Register
Link Control/Bank Select Registers
Beginning Flags/Preamble Length Register
MAX__LEN
34
B4
0
Description
PHY__ERR
B3
0
BAD__CRC
B2
0
OVR1
B1
0
OVR2
B0
0