PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 41

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
3.8.4 LCR/BSR – Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.8.5 IRCFG [1–4] – Infrared Interface Configuration Registers
Four registers are provided to configure the infrared interface. These registers are used to select the infrared receiver inputs as
well as the transceiver operational mode. Selection of the transceiver mode is accomplished by up to three special output signals
(ID/IRSL [2–0]). When these signals are programmed as outputs, they will be forced low when automatic configuration is enabled
(AMCFG bit set to 1) and UART mode is selected.
3.8.5.1 IRCFG1 – Infrared Interface Configuration Register 1
This register holds the transceiver configuration data for Sharp-IR and SIR Modes.
When automatic configuration is not enabled, it is used to directly control the transceiver operational mode. The least significant
four bits are also used to read the identification data of a Plug-n-Play infrared adapter.
B0
B2–1 IRIC[2–1] – Transceiver Identification/Control
B3
B6–4 SIRC [2–0] – SIR Mode Transceiver Configuration.
B7
Reset State
Function
Bits
IRIC0 – Transceiver Identification/Control.
The function of this bit depends on whether the ID0/IRSL0/IRRX2 pin is programmed as an input or as an output.
ID0/IRSL0/IRRX2 Pin Programmed as Input (IRSL0__DS = 0).
ID0/IRSL0/IRRX2 Pin Programmed as Output (IRSL0__DS = 1).
The function of these bits depends on whether the ID/IRSL[2–1] pins are programmed as inputs or as outputs.
ID/IRSL[2–1] Pins Programmed as Inputs (IRSL21__DS = 0).
ID/IRSL[2–1] Pins Programmed as Outputs (IRSL21__DS = 1).
IRID3 – Transceiver Identification.
Upon read, it returns the logic level of the ID3 pin.
Data written into this bit position is ignored.
These bits will drive the ID/IRSL[2–0] pins when AMCFG is 1 and SIR Mode is selected.
They are unused when AMCFG is 0 or when the ID/IRSL[2–0] pins are programmed as inputs.
Upon read, these bits return the values previously written.
STRV__MS – Special Transceiver Mode Select.
This bit is used to select the operational mode in some optical transceiver modules. When this bit is set to 1, the IRTX out-
put is forced high and a timer is started.
The timer times out after approximately 64 µs, at which time the bit is reset and IRTX returns low. The timer is restarted
every time a 1 is written into this bit position. Therefore, the time in which IRTX is forced high can be extended beyond
64 µs.
This should be avoided, however, to prevent damage to the transmitter LED.
Writing 0 into this bit position has no effect.
Upon read, this bit returns the logic level of the pin.
Data written into this bit position is ignored.
If AMCFG is set to 1, this bit will drive the ID0/IRSL0/IRRX2 pin when Sharp-IR Mode is selected.
If AMCFG is 0, this bit will drive the ID0/IRSL0/IRRX2 pin regardless of the selected mode.
Upon read, this bit returns the value previously written.
Upon read, these bits return the logic levels of the pins.
Data written into these bit positions is ignored.
If AMCFG is set to 1, these bits will drive the ID/IRSL[2–1] pins when Sharp-IR Mode is selected.
If AMCFG is 0, these bits will drive the ID/IRSL[2–1] pins regardless of the selected mode.
Upon read, these bits return the values previously written.
STRV__MS
B7
0
SIRC2
FIGURE 31. Infrared Configuration Register 1
B6
0
(Continued)
SIRC1
B5
0
41
SIRC0
B4
0
IRID3
B3
X
IRIC2
B2
X
IRIC1
B1
X
www.national.com
IRIC0
B0
X