PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 27

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
3.3.2 EXCR1 – Extended Control Register 1
Used to control the extended mode of operation.
Upon reset all bits are set to 0.
B0 EXT__SL – Extended Mode Select.
B1 DMANF – DMA Fairness Control.
B2 DMATH – DMA Threshold Levels Select.
B3 DMASWP – DMA Swap.
B4 LOOP – Loopback Enable.
Bits
Function
Reset State
When set to 1, extended mode is selected.
This bit controls the maximum duration of DMA burst transfers.
0
1
An RX__DMA request is deactivated when the RX__FIFO is empty.
This bit selects the TX__FIFO and RX__FIFO threshold levels used by the DMA request logic to support demand transfer
mode.
A TX__DMA request is generated when the TX__FIFO level is below the threshold.
An RX__DMA request is generated when the RX__FIFO level reaches the threshold or when an RX__FIFO time-out occurs.
This bit selects the routing of the DMA control signals between the internal DMA logic and the configuration module. When this
bit is 0, the transmitter and receiver DMA control signals are not swapped. When it is 1, they are swapped. A block diagram
illustrating the control signals routing is given in Figure 16 .
The swap feature is particularly useful when only one 8237 DMA channel is used to serve both transmitter and receiver. In this
case only one external DRQ/DACK signal pair will be interconnected to the swap logic by the configuration module. Routing
the external DMA channel to either the transmitter or the receiver DMA logic is then simply controlled by the DMASWP bit. This
way, the infrared device drivers do not need to know the details of the configuration module.
When set to 1, loopback mode is selected.
This bit accesses the same internal register as bit 4 in the MCR register, when the device is in non-extended mode.
Loopback mode behaves similarly in both non-extended and extended modes.
When extended mode is selected, the DTR bit in the MCR register internally drives both DSR and RI , and the RTS bit drives
CTS and DCD .
During loopback the following occur:
Bit Value
A TX__DMA request is deactivated when the TX__FIFO is full.
DMA requests are forced inactive after approximately 10.5 µs of continuous transmitter and/or receiver DMA operation.
0
1
Baud Rate
Prescaler
Value
1500000
BTEST
115200
230400
460800
750000
921600
B7
57600
0
RX__FIFO DMA Thresh.
TABLE 8. Baud Generator Divisor Settings (Continued)
Divisor
res
B6
0
—
—
—
—
—
10
4
FIGURE 15. Extended Control Register 1
2
1
13
ETDLBK
% Error
B5
(Continued)
0
0.16%
0.16%
—
—
—
—
—
Divisor
LOOP
27
TX__FIFO DMA Thresh.
B4
0
—
—
16
1.625
8
4
2
1
(16-Levels)
DMASWP
% Error
13
7
B3
0.16%
0.16%
0.16%
0.16%
—
0.16%
—
0
Divisor
DMATH
—
—
—
B2
0
26
13
2
1
1
TX__FIFO DMA Thresh.
% Error
DMANF
0.16%
0.16%
—
—
0.00%
—
0.00%
B1
(32-Levels)
0
29
23
EXT__SL
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B0
0