PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 14

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
3.1 BANK 0
3.1.1 TXD/RXD – Transmit/Receive Data Ports
These ports share the same address.
TXD is accessed during CPU write cycles. It provides the write data path to the transmitter holding register when the FIFOs are
disabled, or to the TX__FIFO top location when the FIFOs are enabled.
RXD is accessed during CPU read cycles. It provides the read data path from the receiver holding register when the FIFOs are
disabled, or from the RX__FIFO bottom location when the FIFOs are enabled.
DMA cycles always access the transmitter and receiver holding registers or FIFOs, regardless of the selected bank.
3.1.2 IER – Interrupt Enable Register
This register controls the enabling of the various interrupts. Some interrupts are common to all operating modes, while others are
only available with specific modes. Bits 4 to 7 can be set in extended mode only. They are cleared in non-extended mode. When
a bit is set to 1, an interrupt is generated when the corresponding event occurs. In the non-extended mode most events can be
identified by reading the LSR and MSR registers. The receiver high-data-level event can only be identified by reading the EIR reg-
ister after the corresponding interrupt has been generated. In the extended mode events are identified by event flags in the EIR
register. Upon reset, all bits are set to 0.
Note 1: If the interrupt signal drives an edge-sensitive interrupt controller input, it is advisable to disable all interrupts by clearing all the IER bits upon entering the
interrupt routine, and re-enable them just before exiting it. This will guarantee proper interrupt triggering in the interrupt controller in case one or more interrupt events
occur during execution of the interrupt routine.
Note 2: If an interrupt source must be disabled, the CPU can do so by clearing the corresponding bit in the IER register. However, if an interrupt event occurs just
before the corresponding enable bit in the IER register is cleared, a spurious interrupt may be generated. To avoid this problem, the clearing of any IER bit should
be done during execution of the interrupt service routine. If the interrupt controller is programmed for level-sensitive interrupts, the clearing of IER bits can also be
performed outside the interrupt service routine, but with the CPU interrupt disabled.
Note 3: If the LSR, MSR or EIR registers are to be polled, the interrupt sources which are identified via self-clearing bits should have their corresponding IER bits
set to 0. This will prevent spurious pulses on the interrupt output pin.
B0 RXHDL__IE – Receiver High-Data-Level Interrupt Enable.
B1 TXLDL__IE – Transmitter Low-Data-Level Interrupt Enable.
B2 UART, Sharp-IR, SIR Modes
Bits
Function
Reset State
LS__IE – Link Status Interrupt Enable.
MIR, FIR, CEIR Modes
LS__IE/TXHLT__IE – Link Status/Transmitter Halted Interrupt Enable.
TMR__IE
B7
0
Bank
6
7
Address
Offset
0
1
2
3
4
5
6
7
SFIF__IE TXEMP__IE/
B6
UART
Mode
0
TXD/RXD
IER
EIR/FCR
LCR/BSR
MCR
LSR
MSR
SPR/ASCR
TABLE 1. Register Banks Summary (Continued)
Register
Name
PLD__IE
Mode
FIGURE 5. Interrupt Enable Register
B5
IR
U
U
0
TABLE 2. Bank 0 Register Set
(Continued)
Infrared Physical Layer Configuration
Consumer-IR and Optical Transceiver Configuration
Transmit/Receive Data Ports
Interrupt Enable Register
Event Identification/FIFO Control Registers
Link Control/Bank Select Registers
Modem/Mode Control Register
Link Status Register
Modem Status Register
Scratchpad/Auxiliary Status and Control Register
DMA__IE MS__IE
B4
0
14
B3
0
Description
Description
TXHLT__IE
LS__IE/
B2
0
TXLDL__IE
B1
0
RXHDL__IE
B0
0