PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 22

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

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3.0 Architectural Description
B2 UART, Sharp-IR, SIR Modes
B3 UART, Sharp-IR, SIR Modes
B4 UART, Sharp-IR, SIR Modes
FIFOs Enabled: An overrun occurs when a new character is completely received into the receiver front-end section and the
RX__FIFO is full.
The new character is discarded, and the RX__FIFO is not affected.
MIR, FIR Modes
OE – Overrun Error.
An overrun occurs when a new character is completely received into the receiver front-end section and the RX__FIFO or the
ST__FIFO is full.
The new character is discarded, and the RX__FIFO is not affected.
Cleared upon read.
PE – Parity Error.
This bit is set to 1 if the received character did not have the correct parity, as selected by the parity control bits in the LCR
register.
If the FIFOs are enabled, the Parity Error condition will be associated with the particular character in the RX__FIFO it applies
to.
In which case, the PE bit is set when the character reaches the bottom of the RX__FIFO.
Cleared upon read.
MIR, FIR Modes
BAD__CRC – CRC Error.
Set to 1 when a mismatch between the received CRC and the receiver-generated CRC is detected, and the last byte of the
received frame has reached the bottom of the RX__FIFO.
Cleared upon read.
FE – Framing Error.
This bit indicates that the received character did not have a valid stop bit.
It is set to 1 when the stop bit is detected as a logic 0.
If the FIFOs are enabled, the Framing Error condition will be associated with the particular character in the RX__FIFO it ap-
plies to.
In which case, the FE bit is set when the character reaches the bottom of the RX__FIFO.
After a Framing Error is detected, the receiver will try to resynchronize.
If the bit following the stop bit position is 0, the receiver assumes it to be a valid start bit and the next character is shifted in.
If that bit is 1, the receiver will enter the idle state looking for the next start bit.
Cleared upon read.
MIR Mode
PHY__ERR – Physical Layer Error.
Set to 1 when an abort condition is detected during the reception of a frame, and the last byte of the frame has reached the
bottom of the RX__FIFO.
Cleared upon read.
FIR Mode
PHY__ERR – Physical Layer Error.
Set to 1 when an encoding error or the sequence BOF-data-BOF is detected (missing EOF) during the reception of a frame,
and the last byte of the frame has reached the bottom of the RX__FIFO.
Cleared upon read.
BRK – Break Event Detected.
Set to 1 when a sequence of logic 0 bits, equal or longer than a full character transmission, is received.
If the FIFOs are enabled, the Break condition will be associated with the particular character in the RX__FIFO it applies to.
In which case, the BRK bit is set when the character reaches the bottom of the RX__FIFO. When a Break occurs only one
zero character is transferred to the receiver holding register or to the RX__FIFO.
The next character transfer takes place after at least one logic 1 bit is received followed by a valid start bit.
Cleared upon read.
MIR, FIR Modes
MAX__LEN – Maximum Length.
Set to 1 when a frame exceeding the maximum length has been received, and the last byte of the frame has reached the bot-
tom of the RX__FIFO.
(Continued)
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