PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 21

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

3.0 Architectural Description
B4
B7–5 MDSL [2–0] – Mode Select.
3.1.6 LSR – Link Status Register
This register provides status information to the CPU concerning the data transfer.
Bits 1 through 4 (and 7 when in MIR or FIR mode) indicate link status events.
These bits are sticky, and accumulate any conditions occurred since the last time the register was read.
These bits are cleared when any of the following events occurs:
1. Hardware reset.
2. The receiver is soft reset.
3. The LSR register is read.
Note: This register is intended for read operations only. Writing to this register is not recommended as it may cause indeterminate results.
B0 RXDA – Receiver Data Available.
B1 UART, Sharp-IR, SIR, CEIR Modes
Bits
Function
Reset State
Set to 1 when the Receiver Holding Register is full.
If the FIFOs are enabled, this bit is set when at least one character is in the RX__FIFO.
Cleared when the CPU reads all the data in the Holding Register or in the RX__FIFO.
OE – Overrun Error.
This bit is set to 1 as soon as an overrun condition is detected by the receiver.
Cleared upon read.
FIFOs Disabled: An overrun occurs when a new character is completely received into the receiver front-end section and the
CPU has not yet read the previous character in the receiver holding register. The new character is discarded, and the re-
ceiver holding register is not affected.
When set to 1, transmit deferral is enabled.
Effective only when the TX__FIFO is enabled.
IR__PLS – Send Interaction Pulse.
This bit is effective only in MIR and FIR Modes.
It is set to 1 by writing 1 into it.
Writing 0 into it has no effect.
When set to 1, a 2 µs infrared interaction pulse is transmitted at the end of the frame and the bit is automatically cleared
by the hardware.
This bit is also cleared when the transmitter is soft reset.
Note: The interaction pulse must be emitted at least once every 500 ms, as long as the high-speed connection lasts, in order to quiet slower (115.2 kbps
These bits are used to select the operational mode as shown in Table 5 .
When the mode is changed, the transmitter and receiver are soft reset, and the modem status events are cleared.
or below) systems that might otherwise interfere with the link.
FR__END
ER__INF/
B7
0
TXEMP
7 6 5
Bits
000
001
010
011
100
101
110
111
B6
TABLE 5. UIR Module Operational Modes
1
FIGURE 12. Link Status Register
TXRDY
(Continued)
B5
1
UART
Reserved
Sharp-IR
SIR
MIR
FIR
CEIR
Reserved
MAX__LEN
21
BRK/
B4
0
Operational Mode
PHY__ERR
FE/
B3
0
BAD__CRC
PE/
B2
0
OE
B1
0
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RXDA
B0
0