PC87108AVJE NSC [National Semiconductor], PC87108AVJE Datasheet - Page 45

• Manufacturer Part Number: PC87108AVJE
• Description: Advanced UART and Infrared Controller
• Manufacturer: NSC [National Semiconductor]

4.0 Device Configuration
B7–5 Reserved.
4.2.2 CSRT – Control Signals Routing Register (index = 01h/offset = 09h)
This register is used to select the Interrupt output signal, and the DMA control signals for the device’s receiver and transmitter
communication channels.
B2–0 IRQ__SL [2–0] – IRQ Signal Select.
B4–3 RXD__SL [1–0] – Receiver DMA Control Signals Select.
B6–5 TXD__SL [1–0] – Transmitter DMA Signals Select.
B7
Reset State
Function
Bits
This bit determines whether the IRQ output buffer is configured as Open Drain or Totem Pole.
Read/write as 0.
Selects the IRQ output to be used for interrupt signaling.
After reset, no interrupt is selected, and all the IRQ output pins are in TRI-STATE
These bits determine which external DMA control signals are routed to the internal receiver DMA channel when the
DMASWP bit is 0. Refer to the DMASWP bit description for more information.
These bits determine which external DMA control signals are routed to the internal transmitter DMA channel when the
DMASWP bit is 0. Refer to the DMASWP bit description for more information.
SLERR – DMA Signals Selection Error.
This is a read-only bit. It will be set to 1 if the same DMA control signals are selected for both the transmitter and receiver
channels.
In which case all the DMA control input signals are ignored, and all the DMA control output signals are in TRI-STATE
dition.
SLERR
B7
0
TXD__SL1
B6
0
Encoding
Encoding
FIGURE 36. Control Signals Routing Register
Value
Encoding
00
01
10
11
00
01
10
11
0
1
(Continued)
000
001
010
011
100
101
110
111
TXD__SL0
B5
0
RXD__SL1
45
B4
0
DMA Signals Selected
DMA Signals Selected
Output Buffer Type
DRQ0/DACK0
DRQ1/DACK1
DRQ3/DACK3
DRQ0/DACK0
DRQ1/DACK1
DRQ3/DACK3
Open Drain
Totem Pole
RXD__SL0
IRQ Selected
None
None
B3
IRQ11
IRQ15
None
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
0
IRQ__SL2
®
B2
condition.
0
IRQ__SL1
B1
0
IRQ__SL0
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B0
0
®
con-