AT89C51CC02UA-RATUM Atmel, AT89C51CC02UA-RATUM Datasheet - Page 52

IC 8051 MCU 16K FLASH 32-VQFP

AT89C51CC02UA-RATUM

Manufacturer Part Number
AT89C51CC02UA-RATUM
Description
IC 8051 MCU 16K FLASH 32-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet

Specifications of AT89C51CC02UA-RATUM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
20
Number Of Timers
1
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
CANADAPT28
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Automatic Address
Recognition
Given Address
52
AT/T89C51CC02
Figure 22. UART Timing in Mode 1
Figure 23. UART Timing in Modes 2 and 3
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in the hardware, automatic address recognition enhances the multiproces-
sor communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address will the
receiver set the RI bit in the SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If necessary, the user can enable the automatic address recognition feature in mode 1.
In this configuration, the stop bit takes the place of the ninth data bit. bit RI is set only
when the received command frame address matches the device’s address and is termi-
nated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Each device has an individual address that is specified in the SADDR register; the
SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form
the device’s given address. The don’t-care bits provide the flexibility to address one or
more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SMOD0 = x
SMOD0 = 1
SMOD0 = 0
SMOD0 = 1
SMOD0 = 1
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
RXD
FE
RXD
RI
FE
RI
RI
Start
bit
Start
bit
D0
D0
D1
D1
D2
D2
D3
Data Byte
D3
Data Byte
D4
D4
D5
D5
D6
D6
D7
D7
Stop
bit
Ninth
D8
bit
Stop
4126L–CAN–01/08
bit

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