AT89C51CC02UA-RATUM Atmel, AT89C51CC02UA-RATUM Datasheet - Page 54

• Manufacturer Part Number: AT89C51CC02UA-RATUM
• Description: IC 8051 MCU 16K FLASH 32-VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC02UA-RATUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: CANADAPT28
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Registers
54
AT/T89C51CC02
Table 33. SCON Register
SCON (S:98h)
Serial Control Register
Reset Value = 0000 0000b
bit addressable
Number
FE/SM0
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
SM1
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
RI
6
TI
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Serial port Mode bit 0 (SMOD0 = 0)
Refer to SM1 for serial port mode selection.
Serial port Mode bit 1
SM0 SM1
0
0
1
1
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver bit 8/Ninth bit Received in Modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
Transmit Interrupt Flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
Receive Interrupt Flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, See Figure 22. and
Figure 23. in the other modes.
SM2
5
0
1
0
1
Mode
Shift Register F
8-bit UART
9bit UART
9bit UART
REN
4
Baud Rate
Variable
F
Variable
XTAL
XTAL
TB8
3
/12 (or F
/64 or F
XTAL
XTAL
RB8
/32
/6 in mode X2)
2
TI
1
4126L–CAN–01/08
RI
0