AT89C51CC02UA-RATUM Atmel, AT89C51CC02UA-RATUM Datasheet - Page 84
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AT89C51CC02UA-RATUM
Manufacturer Part Number
AT89C51CC02UA-RATUM
Description
IC 8051 MCU 16K FLASH 32-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.T89C51CC02CA-TDSIM.pdf
(159 pages)
Specifications of AT89C51CC02UA-RATUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
20
Number Of Timers
1
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
CANADAPT28
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89C51CC02UA-RATUM
Manufacturer:
Atmel
Quantity:
1 845
Bit Timing and Baud
Rate
Figure 40. Sample and Transmission Point
84
AT/T89C51CC02
CLOCK
FCAN
Prescaler BRP
FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time
quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.
Field and segment abbreviations:
•
•
•
•
•
•
•
•
The total number of TQ in a bit time has to be programmed at least from 8 to 25.
The baud rate selection is made by Tbit calculation:
Tbit = Tsyns + Tprs + Tphs1 + Tphs2
1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ
2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl
3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl
4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl
5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl
The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to
25.
BRP: Baud Rate Prescaler.
TQ: Time Quantum (output of Baud Rate Prescaler).
SYNS: SYNchronization Segment is 1 TQ long.
PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.
PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
PHS2: PHase Segment 2 is programmable to be superior or eual to the Information
Processing Time and inferior or equal to TPHS1
INFORMATION PROCESSING TIME is 2 TQ.
SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1
and 4.
Tphs2 = Max of (Tphs1 and 2TQ)
System Clock Tscl
Time Quantum
PRS 3bit length
PHS1 3bit length
PHS2 3bit length
SJW 2-bit length
bit Timing
Sample Point
Transmission Point
4126L–CAN–01/08