R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 186

• Manufacturer Part Number: R5F21134DFP#U0
• Description: IC R8C MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/13r

Specifications of R5F21134DFP#U0

• Core Size: 16-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 22
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1024Byte
• Cpu Speed: 20MHz
• No. Of Timers: 16
• Digital Ic Case: RoHS Compliant
• Controller Family/series: R8C/13
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Table 17.4 Software Commands
SRD: Status register data (D
WA: Write address (Make sure the address value specified in the the first bus cycle is the same address
WD: Write data (8 bits)
BA: Given block address
X: Any address in the user ROM area
Read array
Read status register
Clear status register
Block erase
Program
17.4.3 Software Commands
as the write address specified in the second bus cycle.)
• Read Array Command
• Read Status Register Command
• Clear Status Register Command
Software commands are described below. The command code and data must be read and written in
8-bit units.
Jan 27, 2006
This command reads the flash memory.
Writing ‘FF
address in the next or subsequent bus cycles, and the content of the specified address can be read
in 8-bit units.
Because the microcomputer remains in read array mode until another command is written, the con-
tents of multiple addresses can be read in succession.
This command reads the status register.
Write ‘70
to Section 17.4.4, “Status Register.”) When reading the status register too, specify an address in the
user ROM area.
Avoid executing this command in EW1 mode.
This command sets the status register to “0”.
Write ‘50
in the status register will be set to “0”.
Command
16
16
’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5
’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
16
’ in the first bus cycle places the microcomputer in read array mode. Enter the read
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7
to D
Write
Write
Write
Write
Write
Mode
0
)
First bus cycle
Address
WA
X
X
X
X
(D
7
Data
FF
70
50
40
20
to D
16
16
16
16
16
0
)
Mode
Read
Write
Write
Second bus cycle
Address
WA
BA
17.4 CPU Rewrite Mode
X
(D
SRD
D0
Data
7
WD
to D
16
0
)