R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 76
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R5F21134DFP#U0
Manufacturer Part Number
R5F21134DFP#U0
Description
IC R8C MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/13r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21132FPU0.pdf
(33 pages)
3.R5F21132FPU0.pdf
(226 pages)
4.R5F21134DFPU0.pdf
(224 pages)
Specifications of R5F21134DFP#U0
Core Size
16-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
R8C
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
22
Eeprom Memory Size
4KB
Ram Memory Size
1024Byte
Cpu Speed
20MHz
No. Of Timers
16
Digital Ic Case
RoHS Compliant
Controller Family/series
R8C/13
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21134DFP#U0R5F21134DFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 10.15 Key Input Interrupt
Figure 10.16 KIEN Register
10.3 Key Input Interrupt
A key input interrupt is generated on an input edge of any of the K1
be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or disabled
selecting with the KIiEN (i=0 to 3) bit in the KIEN register. The edge polarity can be rising edge or falling
edge selecting with the KIiPL bit in the KIEN register. Note, however, that while input on any KIi pin which
has had the KIiPL bit set to “0” (falling edge) is pulled low, inputs on all other pins of the port are not
detected as interrupts. Similarly, while input on any KIi pin which has had the KIiPL bit set to “1” (rising
edge) is pulled high, inputs on all other pins of the port are not detected as interrupts.
Figure 10.15 shows a block diagram of the key input interrupt.
Jan 27, 2006
Pull-up
transistor
KI
KI
KI
KI
1
0
3
2
K e y i n p u t e n a b l e r e g i s t e r
b 7
N O T E S :
Pull-up
transistor
1 . T h e I R b i t i n t h e K U P I C r e g i s t e r m a y b e s e t t o “ 1 ” ( i n t e r r u p t r e q u e s t e d ) w h e n t h e K I E N r e g i s t e r i s r e w r i t t e n .
Pull-up
transistor
b 6
Pull-up
transistor
R e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 “ C h a n g i n g I n t e r r u p t F a c t o r ” i n t h e U s a g e N o t e s R e f e r e n c e B o o k .
b 5
b 4
page 65 of 205
b 3
b 2
b 1
b 0
B i t s y m b o l
KI0EN
KI1EN
KI2EN
KI3EN
KI0PL
KI1PL
KI2PL
KI3PL
PU02 bit in PUR0 register
PD1_3 bit in PD1 register
KI3PL=0
KI3PL=1
KI2PL=0
KI2PL=1
KI1PL=0
KI1PL=1
KI0PL=0
KI0PL=1
S y m b o l
K I E N
K I 0 i n p u t e n a b l e b i t
K I 0 i n p u t p o l a r i t y s e l e c t b i t
K I 1 i n p u t e n a b l e b i t
K I 1 i n p u t p o l a r i t y s e l e c t b i t
K I 2 i n p u t e n a b l e b i t
K I 2 i n p u t p o l a r i t y s e l e c t b i t
K I 3 i n p u t e n a b l e b i t
K I 3 i n p u t p o l a r i t y s e l e c t b i t
KI3EN bit
KI2EN bit
KI1EN bit
KI0EN bit
PD1_3 bit
PD1_2 bit
PD1_1 bit
PD1_0 bit
B i t n a m e
A d d r e s s
0 0 9 8
1 6
_____
A f t e r r e s e t
0 : D i s a b l e d
1 : E n a b l e d
0 : F a l l i n g e d g e
1 : R i s i n g e d g e s
0 : D i s a b l e d
1 : E n a b l e d
0 : F a l l i n g e d g e
1 : R i s i n g e d g e s
0 : D i s a b l e d
1 : E n a b l e d
0 : F a l l i n g e d g e
1 : R i s i n g e d g e s
0 : D i s a b l e d
1 : E n a b l e d
0 : F a l l i n g e d g e
1 : R i s i n g e d g e s
KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
0 0
1 6
_____
_____
0
Interrupt control circuit
Function
to K1
KUPIC register
_____
3
pins. Key input interrupts can
R W
R W
R W
R W
R W
R W
RW
R W
R W
10.3 Key Input Interrupt
Key input interrupt
request
_____