PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 11

• Manufacturer Part Number: PIC16F785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.0
2.1
The PIC16F785 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space. Only
the first 2k x 14 (0000h–07FFh) for the PIC16F785 is
physically implemented. Accessing a location above
these boundaries will cause a wrap around within the
first 2k x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
 2004 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
INTERRUPT VECTOR
ON-CHIP PROGRAM
RESET VECTOR
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 8
MEMORY
PC<12:0>
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F785
13
000H
0004
0005
07FFH
0800H
1FFFH
Preliminary
2.2
The data memory (see Figure 2-2) is partitioned into
four banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h – 7Fh in Bank 0 and A0h – BFh in Bank 1 are
General Purpose Registers, implemented as static
RAM. The last sixteen register locations in Bank 1
(F0h – FFh), Bank 2 (170h – 17Fh), and Bank 3
(1F0h – 1FFh) point to addresses 70h – 7Fh in Bank 0.
All other RAM is unimplemented and returns ‘0’ when
read.
Seven address bits are required to access any location
in a data memory bank. Two additional bits are required
to access the four banks. When data memory is
accessed directly, the seven least significant address
bits are contained within the opcode and the two most
significant bits are contained in the Status register. RP0
and RP1 (Status<5> and Status<6>) are the two most
significant data memory address bits and are also
known as the bank select bits. Table 2-1 lists how to
access the four banks of registers.
TABLE 2-1:
2.2.1
The register file banks are organized as 128 x 8 in the
PIC16F785. Each register is accessed, either directly,
by seven address bits within the opcode, or indirectly,
through the File Select Register, FSR. When the FSR
is used to access data memory, the eight least signifi-
cant data memory address bits are contained in the
FSR and the ninth most significant address bit is con-
tained in the IRP bit (Status<7>) of the Status register.
(See Section 2.4 “Indirect Addressing, INDF and
FSR Registers”).
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-2). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
Bank0
Bank1
Bank2
Bank3
Data Memory Organization
GENERAL PURPOSE REGISTER
FILE
SPECIAL FUNCTION REGISTERS
BANK SELECTION
RP1
0
0
1
1
PIC16F785
DS41249A-page 9
RP0
0
1
0
1