PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 54

• Manufacturer Part Number: PIC16F785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F785
6.5
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software
(Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples in the PICmicro
Reference Manual (DS33023) show how to read and
write Timer1 when it is running in Asynchronous mode.
TABLE 6-1:
DS41249A-page 52
0Bh,
8Bh
0Ch
0Eh
0Fh
10h
1Ah
8Ch
91h
Legend:
Addr
Note:
INTCON
PIR1
TMR1L
TMR1H
T1CON
CM2CON1 MC1OUT MC2OUT
PIE1
ANSEL0
Timer1 Operation in
Asynchronous Counter Mode
Name
are
The ANSEL0 (91h) register must be initial-
ized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
x = unknown, u = unchanged, — = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
needed
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
REGISTERS ASSOCIATED WITH TIMER1
T1GINV
Bit 7
ANS7
EEIF
EEIE
GIE
to
TMR1GE
®
ANS6
Bit 6
PEIE
ADIF
ADIE
Mid-Range MCU Family
read/write
T1CKPS1
CCP1IF
CCP1IE
ANS5
Bit 5
T0IE
—
the
T1CKPS0
ANS4
Bit 4
INTE
C2IF
C2IE
timer
—
Preliminary
T1OSCEN
ANS3
Bit 3
RAIE
C1IE
C1IF
—
6.6
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low power oscillator rated for 32.768 kHz.
It will continue to run during Sleep. It is primarily
intended for a 32.768 kHz tuning fork crystal.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is also the LP oscillator or is
derived from the internal oscillator. As with the system
LP oscillator, the user must provide a software time
delay to ensure proper oscillator start-up.
SLEEP mode will not disable the system clock when
the system clock and Timer1 share the LP oscillator.
TRISA<5> and TRISA<4> bits are set when the Timer1
oscillator is enabled. RA5 and RA4 read as ‘0’ and
TRISA<5> and TRISA<4> bits read as ‘1’.
6.7
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine (0004h) on an overflow.
If the GIE bit is clear, execution will continue with the
next instruction.
Note:
T1SYNC
OSFIF
OSFIE
Bit 2
ANS2
T0IF
—
Timer1 Oscillator
Timer1 Operation During Sleep
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer 1.
TMR1CS
TMR2IF
TMR2IE
T1GSS
ANS1
Bit 1
INTF
TMR1ON
C2SYNC
TMR1IF
TMR1IE
ANS0
 2004 Microchip Technology Inc.
Bit 0
RAIF
POR, BOR
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
00-- --10
0000 0000
1111 1111
Value on:
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
00-- --10
0000 0000
1111 1111
Value on
all other
Resets