PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 49

IC PIC MCU FLASH 2KX14 20SOIC

PIC16F785-I/SO

Manufacturer Part Number
PIC16F785-I/SO
Description
IC PIC MCU FLASH 2KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F785-I/SO

Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
20-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F785-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 5-1:
 2004 Microchip Technology Inc.
RA2/AN2/T0CKI/INT/C1OUT
Note:
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2-2 on page 16).
SWDTEN
WDTE
(= F
CLKOUT
T0SE
OSC
31 kHz
INTRC
2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2 on page 118).
TIMER0 MODULE
Timer0 Operation
/4)
Additional information on the Timer0
module is available in the PICmicro
Mid-Range
(DS33023).
(1)
Watchdog
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Timer
T0CS
0
1
Reference
(1)
PSA
Prescaler
0
1
16-bit
(1)
Manual ,
WDTPS<3:0>
16
Prescaler
8-bit
Preliminary
®
8
PS<0:2>
(2)
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin RA2/AN2/T0CKI/INT/C1OUT. The incrementing
edge is determined by the source edge (T0SE) control
bit (OPTION_REG<4>). Clearing the T0SE bit selects
the rising edge.
5.2
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit (INTCON<2>). The interrupt
can be masked by clearing the T0IE bit (INTCON<5>).
The T0IF bit must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The Timer0 interrupt cannot wake the
processor from Sleep since the timer is shut-off during
Sleep.
(1)
Note 1: Counter mode has specific external clock
2: The ANSEL0 (91h) register must be
Timer0 Interrupt
PSA
PSA
requirements. Additional information on
these requirements is available in the
PICmicro
Manual , (DS33023).
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
1
0
1
0
(1)
(1)
SYNC 2
Cycles
Time-out
®
WDT
PIC16F785
Mid-Range
Data Bus
Set Flag bit T0IF
DS41249A-page 47
8
TMR0
on Overflow
Reference

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