PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 121

• Manufacturer Part Number: PIC16F785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.7
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit in the Status register is cleared.
• TO bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin, and all
unused peripheral modules should be disabled. Digital
I/O pins that are high-impedance inputs should be
pulled high or low externally to avoid switching currents
caused by floating inputs. The T0CKI input should also
be at V
contribution from on-chip pull-ups on PORTA should be
considered.
The MCLR pin must be at a logic high level.
15.7.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the Status register can be
used to determine the cause of device Reset. The PD
bit, which is set on power-up, is cleared when Sleep is
invoked. TO bit is cleared if WDT Wake-up occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
Other peripherals cannot generate interrupts since,
during Sleep, no on-chip clocks are present.
 2004 Microchip Technology Inc.
SLEEP was executed (driving high, low or high-
impedance).
Note:
External Reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RA2/AN2/T0CKI/INT/C1OUT pin,
PORTA change or a peripheral interrupt.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt
A/D conversion (when A/D clock source is RC)
EEPROM write operation completion
Comparator output changes state
Interrupt-on-change
External Interrupt from INT pin
DD
Power-Down Mode (Sleep)
or V
It should be noted that a Reset generated
by a WDT time out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
SS
for lowest current consumption. The
DD
or V
SS
, with no external
Preliminary
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit (and PIE bit where applicable) must
be set (enabled). Wake-up is regardless of the state of
the GIE bit. If the GIE bit is clear (disabled), the device
continues execution at the instruction after the SLEEP
instruction. If the GIE bit is set (enabled), the device
executes the instruction after the SLEEP instruction,
then branches to the interrupt address (0004h). In
cases where the execution of the instruction following
SLEEP is not desirable, the user should have a NOP
after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
15.7.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
Note:
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
tion of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set, and the PD bit will be cleared.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
WAKE-UP USING INTERRUPTS
PIC16F785
DS41249A-page 119