PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 59

• Manufacturer Part Number: PIC16F785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC5/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF (PIR1<5>) is set.
FIGURE 8-2:
TABLE 8-2:
 2004 Microchip Technology Inc.
0Bh
8Bh
0Ch
0Eh
0Fh
10h
1Ah
13h
14h
15h
87h,
187h
8Ch
Legend:
Addr
RC5/CCP1
Pin
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• set the GO/DONE bit (ADCON0<1>)
Output Enable
TRISC<5>
INTCON
PIR1
TMR1L
TMR1H
T1CON
CM2CON1 MC1OUT MC2OUT
CCPR1L
CCPR1H
CCP1CON
TRISC
PIE1
Compare Mode
Name
Shaded cells are not used by the Capture, Compare or Timer1 module.
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Q
Special Event Trigger
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Capture/Compare/PWM Register1 Low Byte
Capture/Compare/PWM Register1 High Byte
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
CCP1CON<3:0>
T1GINV
TRISC7
R
S
EEIF
EEIE
Bit 7
Mode Select
GIE
—
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set Flag bit CCP1IF
4
TMR1GE
TRISC6
ADIE
Bit 6
PEIE
ADIF
(PIR1<5>)
—
Match
T1CKPS1
CCPR1H CCPR1L
CCP1IE
CCP1IF
TRISC5
DC1B1
TMR1H
Bit 5
T0IE
—
Comparator
TMR1L
T1CKPS0
TRISC4
DC1B0
INTE
C2IE
Bit 4
C2IF
—
Preliminary
T1OSCEN
CCP1M3
TRISC3
RAIE
C1IE
Bit 3
C1IF
—
8.2.1
The user must configure the RC5/CCP1 pin as an
output by clearing the TRISC<5> bit.
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the RC5/CCP1 pin is not
affected. The CCP1IF (PIR1<5>) bit is set, causing a
CCP interrupt (if enabled). See Register 8-1.
8.2.4
In this mode (CCP1M<3:0> = 1011), an internal
hardware trigger is generated, which may be used to
initiate an action. See Register 8-1.
The special event trigger output of CCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1. The special event trigger output also starts an
A/D conversion (if the A/D module is enabled).
Note:
Note:
CCP1M2
T1SYNC
TRISC2
OSFIF
OSFIE
Bit 2
T0IF
—
Clearing the CCP1CON register will force
the RC5/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
The special event trigger from the CCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
CCP1 PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
TMR1CS
CCP1M1
TMR2IE
TMR2IF
TRISC1
T1GSS
Bit 1
INTF
TMR1ON
C2SYNC
CCP1M0
TMR1IF
TMR1IE
TRISC0
RAIF
Bit 0
PIC16F785
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
00-- --10
xxxx xxxx
xxxx xxxx
--00 0000
--11 1111
0000 0000
POR, BOR
Value on:
DS41249A-page 57
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
00-- --10
uuuu uuuu
uuuu uuuu
--00 0000
--11 1111
0000 0000
Value on
all other
Resets