PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 69

• Manufacturer Part Number: PIC16F785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2
The comparator outputs are read through the
CM1CON0, COM2CON0 or CM2CON1 registers.
CM1CON0 and CM2CON0 each contain the individ-
ual comparator output of comparator 1 and compara-
tor 2, respectively. CM2CON2 contains a mirror copy
of both comparator outputs facilitating a simultaneous
read of both comparators. These bits are read-only.
The comparator outputs may also be directly output to
the
RC4/C2OUT/PH2 I/O pins. When enabled, multiplex-
ers in the output path of the RA2 and RC4 pins will
switch and the output of each pin will be the unsyn-
chronized output of the comparator. The uncertainty of
each of the comparators is related to the input offset
voltage and the response time given in the specifica-
tions. Figure 9-1 and Figure 9-2 show the output block
The TRIS bits will still function as an output
enable/disable for the RA2/AN2/T0CKI/INT/C1OUT
and RC4/C2OUT/PH2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C1POL and C2POL bits (CMxCON0<4>).
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS
bit (CM2CON1<1>). The Timer1 gate feature can be
used to time the duration or interval of analog events.
The output of Comparator 2 can also be synchronized
with
(CM2CON1<0>). When enabled, the output of Com-
parator 2 is latched on the falling edge of Timer1 clock
source. If a prescaler is used with Timer1, Comparator
2 is latched after the prescaler. To prevent a race con-
dition, the Comparator 2 output is latched on the falling
edge of the Timer1 clock source and Timer1 incre-
ments on the rising edge of its clock source. See the
Comparator 2 Block Diagram (Figure 9-2) and the
Timer1 Block Diagram (Figure 6-1) for more informa-
tion.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
 2004 Microchip Technology Inc.
diagrams for Comparators 1 and 2, respectively.
Timer1
Comparator Outputs
RA2/AN2/T0CKI/INT/C1OUT
by
setting
the
C2SYNC
and
Preliminary
bit
9.3
The comparator interrupt flags are set whenever there
is a change in the output value of its respective compar-
ator. Software will need to maintain information about
the status of the output bits, as read from
CM2CON0<7:6>, to determine the actual change that
has occurred. The CxIF bits, PIR1<4:3>, are the
Comparator Interrupt Flags. Each comparator interrupt
bit must be reset in software by clearing it to ‘0’. Since
it is also possible to write a ‘1’ to this register, a simu-
lated interrupt may be initiated.
The CxIE bits (PIE1<4:3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CxIF bits will still be set if an interrupt condition occurs.
The comparator interrupt of the PIC16F785 differs from
previous designs in that the interrupt flag is set by the
mismatch edge and not the mismatch level. This
means that the interrupt flag can be reset without the
additional step of reading or writing the CMxCON0
register to clear the mismatch registers. When the
mismatch registers are not cleared, an interrupt will not
occur when the comparator output returns to the
previous state. When the mismatch registers are
cleared, an interrupt will occur when the comparator
returns to the previous state.
9.4
A RESET forces all registers to their RESET state. This
disables both comparators.
Note 1: If a change in the CMxCON0 register
Effects of RESET
2: When either comparator is first enabled,
Comparator Interrupts
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF (PIR1<4:3>)
interrupt flag may not get set.
bias circuitry in the comparator module
may cause an invalid output from the
comparator until the bias circuitry is sta-
ble. Allow about 1 s for bias settling then
clear the mismatch condition and inter-
rupt flags before enabling comparator
interrupts.
PIC16F785
DS41249A-page 67