DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 200

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller
6.3.5
Chip Select Signals
The H8S/2214 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being
driven low when the corresponding external space area is accessed.
Figure 6.3 shows an example of CSn (n = 0 to 7) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular CSn pin.
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals CS1 to CS7.
In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-
on reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7.
For details, see section 9, I/O Ports.
Bus cycle
T
T
T
1
2
3
φ
Address bus
Area n external address
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)
Rev.4.00 Sep. 18, 2008 Page 138 of 872
REJ09B0189-0400