DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 23

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
12.3.4 Operation in
Clocked
Synchronous Mode
Figure 12.23
Sample Serial
Reception Flowchart
Page
515
Revisions (See Manual for Details)
Note added
[3]
No
No
Read receive data in RDR, and
Clear ORER flag in SSR to 0
clear RDRF flag in SSR to 0
Overrun error processing
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
All data received?
Error processing
Start reception
Initialization
ORER = 1
RDRF = 1
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Rev.4.00 Sep. 18, 2008 Page xxi of lx
Yes
[2]
[1]
[3]
[4]
[5]
[1]
[2] [3]
[4]
[5]
Note: * The RDRF flag is cleared
The RxD pin is automatically
designated as the receive data
input pin.
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
processing, clear the ORER flag
to 0. Transfer cannot be resumed
if the ORER flag is set to 1.
SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC* is activated by a receive
data full interrupt (RXI) request
and the RDR value is read.
SCI initialization:
Receive error processing:
automatically by DTC only
when the DTC DISEL bit is 0
and furthermore the transfer
counter is not 0. Therefore
the CPU must clear the
RDRF flag when either
DISEL is 1 or when DISEL is
0 and furthermore the
transfer counter is 0.
REJ09B0189-0400