DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 28

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
B.2 Functions
TCR2—Timer
Control Register 2
TCSR0—Timer
Control/Status
Register
Rev.4.00 Sep. 18, 2008 Page xxvi of lx
REJ09B0189-0400
Page
791
801
Revisions (See Manual for Details)
Description added
Clock Edge 1 and 0
Note added
Notes: 1.
Note: The internal clock edge selection is valid when the input clock is
0
1
Bit
Initial value
Read/Write
Overflow Flag
—
0
1
0
1
2.
[Clearing condition]
• Cleared by reading*
[Setting condition]
• When TCNT overflows (changes from H'FF to H'00)
φ/4 or slower. This setting is ignored if the input clock is φ/1, or
when overflow/underflow of another channel is selected.
(Counting occurs on the falling edge of φ when φ/1 is selected.)
Count at rising edge
Count at falling edge
Count at both edges
When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.
Only 0 can be written, to clear the flag.
TCSR is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.
If the interval timer interrupt is disabled and the OVF flag is polled, the application
should read the OVF = 1 state at least twice.
Note: * For details of the case where TCNT overflows in watchdog timer mode,
Timer Mode Select
0
1
R/(W)*
OVF
Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when
TCNT overflows
Watchdog timer mode: Internal reset can be selected when TCNT overflows*
7
0
see section 11.2.3, Reset Control/Status Register (RSTCSR).
1
Timer Enable
0
1
2
WT/IT
R/W
TCNT is initialized to H'00 and
count operation is halted
TCNT counts
TCSR when OVF = 1, then writing 0 to OVF
6
0
Clock Select 2 to 0
Note: * The overflow period is the time from when TCNT
CKS2 CKS1 CKS0
0
1
TME
R/W
5
0
0
1
0
1
starts counting up from H'00 until overflow occurs.
—
—
4
1
0
1
0
1
0
1
0
1
Clock
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
—
—
3
1
CKS2
R/W
2
0
Overflow Period*
(when φ = 10 MHz)
51.2 µs
1.6 ms
3.2 ms
13.2 ms
52.4 ms
209.8 ms
838.8 ms
3.36 s
CKS1
R/W
1
0
CKS0
R/W
0
0