DF2214BQ16V Renesas Electronics America, DF2214BQ16V Datasheet - Page 38

• Manufacturer Part Number: DF2214BQ16V
• Description: IC H8S/2214 MCU FLASH 112-TFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2214BQ16V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-TFBGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2218 - DEV EVAL KIT H8S/2218
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.6
7.7
Section 8 Data Transfer Controller (DTC) ........................................................251
8.1
8.2
8.3
Rev.4.00 Sep. 18, 2008 Page xxxvi of lx
REJ09B0189-0400
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMAC Multi-Channel Operation ......................................................................... 240
7.5.11 Relation between the DMAC, External Bus Requests, and the DTC ................... 242
7.5.12 NMI Interrupts and DMAC .................................................................................. 243
7.5.13 Forced Termination of DMAC Operation............................................................. 244
7.5.14 Clearing Full Address Mode................................................................................. 245
Interrupts............................................................................................................................ 246
Usage Notes ....................................................................................................................... 247
Overview............................................................................................................................ 251
8.1.1
8.1.2
8.1.3
Register Descriptions ......................................................................................................... 254
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation ........................................................................................................................... 262
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10 Number of DTC Execution States ........................................................................ 275
8.3.11 Procedures for Using DTC.................................................................................... 277
Repeat Mode ......................................................................................................... 217
Normal Mode........................................................................................................ 221
Block Transfer Mode ............................................................................................ 224
DMAC Activation Sources ................................................................................... 230
Basic DMAC Bus Cycles...................................................................................... 232
DMAC Bus Cycles (Dual Address Mode)............................................................ 233
Features................................................................................................................. 251
Block Diagram...................................................................................................... 252
Register Configuration.......................................................................................... 253
DTC Mode Register A (MRA) ............................................................................. 254
DTC Mode Register B (MRB).............................................................................. 256
DTC Source Address Register (SAR)................................................................... 257
DTC Destination Address Register (DAR)........................................................... 257
DTC Transfer Count Register A (CRA) ............................................................... 258
DTC Transfer Count Register B (CRB)................................................................ 258
DTC Enable Register (DTCER) ........................................................................... 259
DTC Vector Register (DTVECR)......................................................................... 260
Module Stop Control Register A (MSTPCRA) .................................................... 261
Overview............................................................................................................... 262
Activation Sources................................................................................................ 264
DTC Vector Table ................................................................................................ 265
Location of Register Information in Address Space ............................................. 268
Normal Mode........................................................................................................ 269
Repeat Mode ......................................................................................................... 270
Block Transfer Mode ............................................................................................ 271
Chain Transfer ...................................................................................................... 273
Operation Timing.................................................................................................. 274