D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 115
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3.4
3.4.1
There are two kinds of MMU hardware management as follows:
1. The MMU decodes the virtual address accessed by a process and performs address translation
2. In address translation, the MMU receives page management information from the TLB, and
3.4.2
There are three kinds of MMU software management, as follows.
1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2
2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by
3. MMU exception processing. When an MMU exception is generated, it is handled on the basis
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be created in the privileged mode only.
Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4,
Avoiding Synonym Problems.
by controlling the TLB in accordance with the MMUCR settings.
determines the MMU exception and whether the cache is to be accessed (using the C bit). For
details of the determination method and the hardware processing, see section 3.5, MMU
Exceptions.
for which address translation is not performed. Also, since SV and IX bit changes constitute
address translation system changes, in this case, TLB flushing should be performed by
simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the
MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided
with software that does not use the MMU.
using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB
entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3,
MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6,
Configuration of Memory-Mapped TLB, for details of the memory-mapped TLB.
of information set from the hardware side. See section 3.5, MMU Exceptions, for details.
MMU Functions
MMU Hardware Management
MMU Software Management
Rev. 5.00, 09/03, page 69 of 760
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