D6417709SF167BV Renesas Electronics America, D6417709SF167BV Datasheet - Page 596
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123112/d6417709sf167bv_sml.jpg)
D6417709SF167BV
Manufacturer Part Number
D6417709SF167BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SF167BV
Core Processor
SH-3
Core Size
32-Bit
Speed
167MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SF167BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.4
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive-data-full (RXI), and break (BRI).
Table 16.10 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE and RIE bits in SCSCR. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is
generated. The DMAC can be activated and data transfer performed when this interrupt is
generated. When data exceeding the transmit trigger number is written to the transmit data register
(SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to clear it.
When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can
be activated and data transfer performed when the RDF flag in SCSSR is set to 1. When receive
data less than the receive trigger number is read from the receive data register (SCFRDR) by the
DMAC, 1 is read from the RDF flag, after which 0 is written to it to clear it.
When the ER flag in SCSSR is set to 1, an ERI interrupt request is generated.
When the BRK flag in SCSSR is set to 1, a BRI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
Table 16.10 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
See section 4, Exception Handling, for priorities and the relationship to non-SCIF interrupts.
Rev. 5.00, 09/03, page 550 of 760
SCIF Interrupts
Description
Interrupt initiated by receive error flag (ER)
Interrupt initiated by receive data FIFO full flag
(RDF) or data ready flag (DR)
Interrupt initiated by break flag (BRK)
Interrupt initiated by transmit FIFO data empty
flag (TDFE)
DMAC
Activation
Not possible
Possible
(RDF only)
Not possible
Possible
Priority on
Reset Release
High
Low
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